/*
 * Copyright (c) 2022, IMMORTA Inc. All rights reserved. Redistribution and use in source and binary fo
 * rms, with or without modification, are permitted provided that the following conditions are met: - R
 * edistributions of source code must retain the above copyright notice, this list of conditions and th
 * e following disclaimer. - Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation and/or other materials pro
 * vided with the distribution. - Neither the name of IMMORTA Inc. nor the names of its contributors ma
 * y be used to endorse or promote products derived from this software without specific prior written p
 * ermission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRE
 * SS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY A
 * ND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRI
 * BUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR P
 * ROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT
 * , STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * @file     IM94.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     21. July 2022
 * @note     Generated by SVDConv V3.3.35 on Thursday, 21.07.2022 17:31:17
 *           from File 'IM94.svd',
 *           last modified on Thursday, 21.07.2022 08:50:20
 */



/** @addtogroup IMMORTA
  * @{
  */


/** @addtogroup IM94
  * @{
  */


#ifndef IM94_H
#define IM94_H

// #ifdef __cplusplus
// extern "C" {
// #endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  NonMaskableInt_IRQn       =  -14,            /*!< Non Maskable Interrupt                                                     */
  HardFault_IRQn            =  -13,            /*!< Cortex-M4 SV Hard Fault Interrupt                                          */
  MemoryManagement_IRQn     =  -12,            /*!< Cortex-M4 Memory Management Interrupt                                      */
  BusFault_IRQn             =  -11,            /*!< Cortex-M4 Bus Fault Interrupt                                              */
  UsageFault_IRQn           =  -10,            /*!< Cortex-M4 Usage Fault Interrupt                                            */
  SVCall_IRQn               =  -5,             /*!< Cortex-M4 SV Call Interrupt                                                */
  DebugMonitor_IRQn         =  -4,             /*!< Cortex-M4 Debug Monitor Interrupt                                          */
  PendSV_IRQn               =  -2,             /*!< Cortex-M4 Pend SV Interrupt                                                */
  SysTick_IRQn              =  -1,             /*!< Cortex-M4 System Tick Interrupt                                            */
/* ==========================================  IM94 Specific Interrupt Numbers  ============================================== */
  WDG_IRQn                 =  0,               /*!< 0 WDG                                                                      */
  ERM_Error_IRQn            =  1,              /*!< 1 ERM_Error                                                                */
  LVD_IRQn                  =  2,              /*!< 2 LVD                                                                      */
  CLOCK_Fault_IRQn          =  3,              /*!< 3 CLOCK_Fault                                                              */
  DMA_Channel0_IRQn         =  4,              /*!< 4 DMA_Channel0                                                             */
  DMA_Channel1_IRQn         =  5,              /*!< 5 DMA_Channel1                                                             */
  DMA_Channel2_IRQn         =  6,              /*!< 6 DMA_Channel2                                                             */
  DMA_Channel3_IRQn         =  7,              /*!< 7 DMA_Channel3                                                             */
  DMA_Channel4_IRQn         =  8,              /*!< 8 DMA_Channel4                                                             */
  DMA_Channel5_IRQn         =  9,              /*!< 9 DMA_Channel5                                                             */
  DMA_Channel6_IRQn         =  10,             /*!< 10 DMA_Channel6                                                            */
  DMA_Channel7_IRQn         =  11,             /*!< 11 DMA_Channel7                                                            */
  GPIOA_IRQn                =  16,             /*!< 16 GPIOA                                                                   */
  GPIOB_IRQn                =  17,             /*!< 17 GPIOB                                                                   */
  GPIOC_IRQn                =  18,             /*!< 18 GPIOC                                                                   */
  GPIOD_IRQn                =  19,             /*!< 19 GPIOD                                                                   */
  GPIOE_IRQn                =  20,             /*!< 20 GPIOE                                                                   */
  RTC_IRQn                  =  22,             /*!< 22 RTC                                                                     */
  TIMER0_IRQn               =  23,             /*!< 23 TIMER0                                                                  */
  TIMER1_IRQn               =  24,             /*!< 24 TIMER1                                                                  */
  TIMER2_IRQn               =  25,             /*!< 25 TIMER2                                                                  */
  TIMER3_IRQn               =  26,             /*!< 26 TIMER3                                                                  */
  SPI0_IRQn                 =  27,             /*!< 27 SPI0                                                                    */
  SPI1_IRQn                 =  28,             /*!< 28 SPI1                                                                    */
  SPI2_IRQn                 =  29,             /*!< 29 SPI2                                                                    */
  SPI3_IRQn                 =  30,             /*!< 30 SPI3                                                                    */
  I2C0_IRQn                 =  31,             /*!< 31 I2C0                                                                    */
  I2C1_IRQn                 =  32,             /*!< 32 I2C1                                                                    */
  UART0_IRQn                =  33,             /*!< 33 UART0                                                                   */
  UART1_IRQn                =  34,             /*!< 34 UART1                                                                   */
  UART2_IRQn                =  35,             /*!< 35 UART2                                                                   */
  UART3_IRQn                =  36,             /*!< 36 UART3                                                                   */
  CAN0_IRQn                 =  39,             /*!< 39 CAN0                                                                    */
  CAN1_IRQn                 =  40,             /*!< 40 CAN1                                                                    */
  CAN2_IRQn                 =  41,             /*!< 41 CAN2                                                                    */
  ADC0_IRQn                 =  45,             /*!< 45 ADC0                                                                    */
  ADC1_IRQn                 =  46,             /*!< 46 ADC1                                                                    */
  CMP0_IRQn                 =  47,             /*!< 47 CMP0                                                                    */
  IPWM0_Channel_IRQn        =  48,             /*!< 48 IPWM0_Channel                                                           */
  IPWM0_Overflow_IRQn       =  49,             /*!< 49 IPWM0_Overflow                                                          */
  IPWM1_Channel_IRQn        =  50,             /*!< 50 IPWM1_Channel                                                           */
  IPWM1_Overflow_IRQn       =  51,             /*!< 51 IPWM1_Overflow                                                          */
  SPWM0_Channel_IRQn        =  52,             /*!< 52 SPWM0_Channel                                                           */
  SPWM0_Fault_IRQn          =  53,             /*!< 53 SPWM0_Fault                                                             */
  SPWM0_Overflow_IRQn       =  54,             /*!< 54 SPWM0_Overflow                                                          */
  SPWM1_Channel_IRQn        =  55,             /*!< 55 SPWM1_Channel                                                           */
  SPWM1_Fault_IRQn          =  56,             /*!< 56 SPWM1_Fault                                                             */
  SPWM1_Overflow_IRQn       =  57,             /*!< 57 SPWM1_Overflow                                                          */
  SPWM2_Channel_IRQn        =  58,             /*!< 58 SPWM2_Channel                                                           */
  SPWM2_Fault_IRQn          =  59,             /*!< 59 SPWM2_Fault                                                             */
  SPWM2_Overflow_IRQn       =  60,             /*!< 60 SPWM2_Overflow                                                          */
  MBOX_IRQn                 =  62,             /*!< 62 HSM_Mbox                                                                */
  HSM_Error_IRQn            =  63,             /*!< 63 HSM_Error                                                               */
} IRQn_Type;


/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  ============================ */
#define __CM4_REV                      0x0000U  /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               4        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  1        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */

/* =========================================================================================================================== */
/* ================                                           RESET                                           ================ */
/* =========================================================================================================================== */

/**
  * @brief Reset control module (RESET)
  */

typedef struct {                                /*!< (@ 0x40000000) RESET Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */
  __IOM uint32_t  FCR;                          /*!< (@ 0x00000004) Filter Control Register                                    */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000008) Status Register                                            */
} RESET_Type;                                   /*!< Size = 12 (0xc)                                                           */


/* =========================================================================================================================== */
/* ================                                           CLOCK                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Clock generate and control module (CLOCK)
  */

typedef struct {                                /*!< (@ 0x40001000) CLOCK Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */
  __IOM uint32_t  XOSCCR;                       /*!< (@ 0x00000004) XOSC Control Register                                      */
  __IOM uint32_t  PLLCR;                        /*!< (@ 0x00000008) PLL Control Register                                       */
  __IOM uint32_t  SR;                           /*!< (@ 0x0000000C) Status Register                                            */
  __IOM uint32_t  AHBPCCR;                      /*!< (@ 0x00000010) AHB Peripheral Clock Control Register                      */
  __IOM uint32_t  APBPCCR;                      /*!< (@ 0x00000014) APB Peripheral Clock Control Register                      */
  __IOM uint32_t  AHBPSRR;                      /*!< (@ 0x00000018) AHB Peripheral Software Reset Register                     */
  __IOM uint32_t  APBPSRR;                      /*!< (@ 0x0000001C) APB Peripheral Software Reset Register                     */
  __IOM uint32_t  PFCSR;                        /*!< (@ 0x00000020) Peripheral Function Clock Selection Register               */
} CLOCK_Type;                                   /*!< Size = 36 (0x24)                                                          */

/* =========================================================================================================================== */
/* ================                                            ERM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Error Report Module (ERM)
  */

typedef struct {                                /*!< (@ 0x40082000) ERM Structure                                              */
  __IOM uint32_t  SCR;                          /*!< (@ 0x00000000) ERM SRAM Control Register                                  */
  __IOM uint32_t  SSR;                          /*!< (@ 0x00000004) ERM SRAM Status Register                                   */
  __IM  uint32_t  SSEA;                         /*!< (@ 0x00000008) ERM SRAM Single-bit error Address Register                 */
  __IM  uint32_t  SNEA;                         /*!< (@ 0x0000000C) ERM SRAM Non-correctable Error Address Register            */
  __IOM uint32_t  PFCR;                         /*!< (@ 0x00000010) ERM P-Flash Control Register                               */
  __IOM uint32_t  PFSR;                         /*!< (@ 0x00000014) ERM P-Flash Status Register                                */
  __IM  uint32_t  PFSEA;                        /*!< (@ 0x00000018) ERM P-Flash Single-bit error Address Register              */
  __IM  uint32_t  PFNEA;                        /*!< (@ 0x0000001C) ERM P-Flash Non-correctable error Address Register         */
  __IOM uint32_t  DFCR;                         /*!< (@ 0x00000020) ERM D-Flash Control Register                               */
  __IOM uint32_t  DFSR;                         /*!< (@ 0x00000024) ERM D-Flash Status Register                                */
  __IM  uint32_t  DFSEA;                        /*!< (@ 0x00000028) ERM D-Flash Single-bit error Address Register              */
  __IM  uint32_t  DFNEA;                        /*!< (@ 0x0000002C) ERM D-Flash Non-correctable error Address Register         */
} ERM_Type;                                     /*!< Size = 48 (0x30)                                                          */



/* =========================================================================================================================== */
/* ================                                          DMA                                              ================ */
/* =========================================================================================================================== */


/**
  * @brief Direct Memory Access (DMA)
  */
typedef struct {                            /*!< (@ 0x40008000) DMA Structure                                                 */
    __IOM uint32_t  GLB_ENABLE;             /*!< (@ 0x00000000) DMA Global Enable Register                                    */
    __IM  uint32_t  CH_ENABLE;              /*!< (@ 0x00000004) DMA Channel Enable Register                                   */
    __IOM uint32_t  SWREQ;                  /*!< (@ 0x00000008) DMA Software Request Register                                 */
} DMA_Type;                                 /*!< Size = 12 (0xc)                                                              */

/* =========================================================================================================================  */
/* ================                                        DMA_CH                                        ===================  */
/* ===========================================================================================================================*/


/**
  * @brief DMA Channel Register (DMA_CH)
  */

typedef struct {                                /*!< (@ 0x40008020) DMA_CH Structure                                           */
  __IOM uint32_t  CHSRC;                        /*!< (@ 0x00000000) DMA Channel Source Address Register                        */
  __IOM uint32_t  CHDST;                        /*!< (@ 0x00000004) DMA Channel Destination Address Register                   */
  __IOM uint32_t  CHLLI;                        /*!< (@ 0x00000008) DMA Channel Linked List Address Register                   */
  __IOM uint32_t  CHCR;                         /*!< (@ 0x0000000C) DMA Channel Control Register                               */
  __IOM uint32_t  CHCONF;                       /*!< (@ 0x00000010) DMA Channel Configuration Register                         */
  __IOM uint32_t  CHSR;                         /*!< (@ 0x00000014) DMA Channel Status Register                                */
} DMA_CH_Type;                                  /*!< Size = 24 (0x18)                                                          */

/* =========================================================================================================================== */
/* ================                                        UART                                        ======================= */
/* =========================================================================================================================== */

/**
  * @brief Universal Asynchronous Receiver/Transmitter (UART)
  */

typedef struct {                                /*!< (@ 0x40017000) UART Structure                                             */
  __IOM uint32_t  UCR;                          /*!< (@ 0x00000000) UART Configure Register                                    */
  __IOM uint32_t  LCR;                          /*!< (@ 0x00000004) LIN Control Register*                                      */
  __IOM uint32_t  BAUD;                         /*!< (@ 0x00000008) Buadrate Configure Register                                */
  __IOM uint32_t  IER;                          /*!< (@ 0x0000000C) Interrupt Configure Register                               */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) State Configure Register                                   */
  __IOM uint32_t  DATA;                         /*!< (@ 0x00000014) Uart Data Register                                         */
} UART_Type;


/* =========================================================================================================================== */
/* ================                                           IPWM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Independent Pulse Width Modulation Module (IPWM)
  */

typedef struct {                                /*!< (@ 0x40085000) IPWM Structure                                            */
  __IOM uint32_t  GPSC;                         /*!< (@ 0x00000000) Global Clock Prescaler                                     */
  __IOM uint32_t  CNTSC[4];                     /*!< (@ 0x00000004) Counter (n) Status And Control                             */
  __IOM uint32_t  CHCNT[4];                     /*!< (@ 0x00000014) Channel (n) Counter Value                                  */
  __IOM uint32_t  CHMOD[4];                     /*!< (@ 0x00000024) Channel (n) Modulo Value                                   */
  __IOM uint32_t  CHCNTIN[4];                   /*!< (@ 0x00000034) Channel (n) Counter Initial Value                          */
  __IOM uint32_t  CHSC[4];                      /*!< (@ 0x00000044) Channel (n) Status And Control                             */
  struct {
    __IOM uint32_t  CVa;                        /*!< (@ 0x00000054) Channel (n) Value a                                        */
    __IOM uint32_t  CVb;                        /*!< (@ 0x00000058) Channel (n) Value b                                        */
  }CHVAL[4];
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000074) Match And Capture Status                                   */
  __IOM uint32_t  MODE;                         /*!< (@ 0x00000078) Features Mode Selection                                    */
  __IOM uint32_t  SYNC;                         /*!< (@ 0x0000007C) Synchronization                                            */
  __IOM uint32_t  OUTINIT;                      /*!< (@ 0x00000080) Initial State For Channels Output                          */
  __IOM uint32_t  OUTMASK;                      /*!< (@ 0x00000084) Output Mask                                                */
  __IOM uint32_t  SWOCTRL;                      /*!< (@ 0x00000088) PWM Software Output Control                                */
  __IOM uint32_t  EXTTRIG;                      /*!< (@ 0x0000008C) PWM External Trigger                                       */
  __IOM uint32_t  FILTER;                       /*!< (@ 0x00000090) Input Capture Filter Control                               */
  __IOM uint32_t  QDCTRL;                       /*!< (@ 0x00000094) Quadrature Decoder Control And Status                      */
  __IOM uint32_t  POL;                          /*!< (@ 0x00000098) Channels Polarity                                          */
  __IOM uint32_t  SYNCONF;                      /*!< (@ 0x0000009C) Synchronization Configuration                              */
  __IOM uint32_t  CONF;                         /*!< (@ 0x000000A0) Configuration                                              */
  struct {
    __IOM uint32_t  CVaDITHER;                  /*!< (@ 0x000000A4) Channel (n) Match Value a Dither Value                     */
    __IOM uint32_t  CVbDITHER;                  /*!< (@ 0x000000A8) Channel (n) Match Value b Dither Value                     */
  }CHDITHER[4];
  __IOM uint32_t  CHMODDITHER[4];               /*!< (@ 0x000000C4) Channel (n) Modulo Dither Value                            */
} IPWM_Type;                                    /*!< Size = 176 (0xb0)                                                         */

/* =========================================================================================================================== */
/* ================                                           SPWM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Share Pulse Width Modulation Module (SPWM)
  */

typedef struct {                                /*!< (@ 0x40087000) SPWM Structure                                             */
  __IOM uint32_t  SC;                           /*!< (@ 0x00000000) Status And Control                                         */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000004) Counter Value                                              */
  __IOM uint32_t  MOD;                          /*!< (@ 0x00000008) Modulo Value                                               */
  __IOM uint32_t  CNTIN;                        /*!< (@ 0x0000000C) Counter Initial Value                                      */
  struct {
    __IOM uint32_t  CnSC;                       /*!< (@ 0x00000010) Channel (n) Status And Control Register                    */
    __IOM uint32_t  CnV;                        /*!< (@ 0x00000014) Channel (n) Value                                          */
  } CONTROLS[8];
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000050) Capture And Compare Status                                 */
  __IOM uint32_t  MODE;                         /*!< (@ 0x00000054) Features Mode Selection                                    */
  __IOM uint32_t  SYNC;                         /*!< (@ 0x00000058) Synchronization                                            */
  __IOM uint32_t  OUTINIT;                      /*!< (@ 0x0000005C) Initial State For Channels Output                          */
  __IOM uint32_t  OUTMASK;                      /*!< (@ 0x00000060) Output Mask                                                */
  __IOM uint32_t  COMBINE;                      /*!< (@ 0x00000064) Function For Linked Channels                               */
  __IOM uint32_t  EXTTRIG;                      /*!< (@ 0x00000068) PWM External Trigger                                       */
  __IOM uint32_t  POL;                          /*!< (@ 0x0000006C) Channels Polarity                                          */
  __IOM uint32_t  FMS;                          /*!< (@ 0x00000070) Fault Mode Status                                          */
  __IOM uint32_t  FILTER;                       /*!< (@ 0x00000074) Input Capture Filter Control                               */
  __IOM uint32_t  FLTCTRL;                      /*!< (@ 0x00000078) Fault Control                                              */
  __IOM uint32_t  CONF;                         /*!< (@ 0x0000007C) Configuration                                              */
  __IOM uint32_t  FLTPOL;                       /*!< (@ 0x00000080) PWM Fault Input Polarity                                   */
  __IOM uint32_t  SYNCONF;                      /*!< (@ 0x00000084) Synchronization Configuration                              */
  __IOM uint32_t  INVCTRL;                      /*!< (@ 0x00000088) PWM Inverting Control                                      */
  __IOM uint32_t  SWOCTRL;                      /*!< (@ 0x0000008C) PWM Software Output Control                                */
  __IOM uint32_t  DEADTIME0;                    /*!< (@ 0x00000090) Deadtime Configuration0                                    */
  __IOM uint32_t  DEADTIME1;                    /*!< (@ 0x00000094) Deadtime Configuration1                                    */
  __IOM uint32_t  CHDITHER[8];                  /*!< (@ 0x00000098) Channel Dither 0                                           */
  __IOM uint32_t  MODDITHER;                    /*!< (@ 0x000000B8) Modulo Dither                                              */
} SPWM_Type;                                    /*!< Size = 164 (0xa4)                                                         */

/* =========================================================================================================================== */
/* ================                                           ADC                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog-to-Digital Converter (ADC)
  */

typedef struct {                                 /*!< (@ 0x40006000) ADC0 Structure                                             */
  __IOM uint32_t  SR0;                           /*!< (@ 0x00000000) ADC Status Register 0                                      */
  __IOM uint32_t  SR1;                           /*!< (@ 0x00000004) ADC Status Register 1                                      */
  __IOM uint32_t  SR2;                           /*!< (@ 0x00000008) ADC Status Register 2                                      */
  __IOM uint32_t  CR0;                           /*!< (@ 0x0000000C) ADC Control Register 0                                     */
  __IOM uint32_t  POFR[4];                       /*!< (@ 0x00000010) Priority Channel Sequence n Data Offset Register           */
  struct {
    __IOM uint32_t  HTR;                         /*!< (@ 0x00000020) ADC Analog Watchdog n High Threshold Register              */
    __IOM uint32_t  LTR;                         /*!< (@ 0x00000024) ADC Analog Watchdog n Low Threshold Register               */
  }AWD[4];
  __IOM uint32_t  NSQR[20];                      /*!< (@ 0x00000040) ADC Normal Channel Sequence n Register                     */
        uint8_t RESERVED_0[48];
  __IOM uint32_t  PSQR[4];                       /*!< (@ 0x000000C0) ADC Priority Channel Sequence n Register                   */
  __IOM uint32_t  NDR[20];                       /*!< (@ 0x000000D0) ADC Normal Channel Sequence n Data Register                */
        uint8_t RESERVED_1[48];
  __IOM uint32_t  PDR[4];                        /*!< (@ 0x00000150) ADC Priority Channel Sequence n Data Register              */
} ADC_Type;                                      /*!< Size = 352 (0x160)                                                        */
/* =========================================================================================================================== */
/* ================                                            ICM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Internal Connection Module (ICM)
  */

typedef struct {                                /*!< (@ 0x40006000) ICM Structure                                              */
  __IOM uint32_t  CR0;                          /*!< (@ 0x00000000) ICM Control Register 0                                     */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000004) ICM Control Register 1                                     */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000008) ICM Control Register 2                                     */
  __IOM uint32_t  CR3;                          /*!< (@ 0x0000000C) ICM Control Register 3                                     */
  __IOM uint32_t  CR4;                          /*!< (@ 0x00000010) ICM Control Register 4                                     */
  __IOM uint32_t  CR5;                          /*!< (@ 0x00000014) ICM Control Register 5                                     */
} ICM_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real Time Clock (RTC)
  */

typedef struct {                                /*!< (@ 0x40007000) RTC Structure                                              */
  __IOM uint32_t  CFG;                          /*!< (@ 0x00000000) RTC Configuration Register                                 */
  __IOM uint32_t  ALM;                          /*!< (@ 0x00000004) RTC Alarm Register                                         */
  __IOM uint32_t  PALM;                         /*!< (@ 0x00000008) RTC Periodic Alarm Register                                */
  __IOM uint32_t  PSCAL;                        /*!< (@ 0x0000000C) RTC Prescaler Register                                     */
  __IOM uint32_t  ICOMP;                        /*!< (@ 0x00000010) RTC Interval Compensation Register                         */
  __IOM uint32_t  INT;                          /*!< (@ 0x00000014) RTC Interrupt Configuration Register                       */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000018) RTC Status Register                                        */
  __IOM uint32_t  SCNT;                         /*!< (@ 0x0000001C) RTC Second Counter Register                                */
} RTC_Type;                                     /*!< Size = 32 (0x20)                                                          */

/* =========================================================================================================================== */
/* ================                                           WDOG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Watchdog (WDG)
  */

typedef struct {                                /*!< (@ 0x40052000) WDOG Structure                                             */
  __IOM uint32_t  CS;                           /*!< (@ 0x00000000) Watchdog Control and Status Register                       */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000004) Watchdog Counter Register                                  */
  __IOM uint32_t  TOVAL;                        /*!< (@ 0x00000008) Watchdog Timeout Value Register                            */
  __IOM uint32_t  WIN;                          /*!< (@ 0x0000000C) Watchdog Window Register                                   */
} WDG_Type;                                     /*!< Size = 16 (0x10)                                                          */


/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief FLASH (FLASH)
  */

typedef struct {                                /*!< (@ 0x40010000) FLASH Structure                                            */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000000) Flash Status Register                                      */
  __IOM uint32_t  LCSR;                         /*!< (@ 0x00000004) Flash Lock Control and Status Register                     */
  __IOM uint32_t  PKEY;                         /*!< (@ 0x00000008) Program Flash Key Register                                 */
  __IOM uint32_t  DKEY;                         /*!< (@ 0x0000000C) Data Flash Key Register                                    */
  __IOM uint32_t  OKEY;                         /*!< (@ 0x00000010) Option Bytes Key Register                                  */
  __IOM uint32_t  CFGR;                         /*!< (@ 0x00000014) Flash Configuration Register                               */
  __IOM uint32_t  CCR;                          /*!< (@ 0x00000018) Flash Command Control Register                             */
  __IOM uint32_t  ADDR;                         /*!< (@ 0x0000001C) Flash Command Start Address Register                       */
  __IOM uint32_t  DATAH;                        /*!< (@ 0x00000020) Flash Program Data High Register                           */
  __IOM uint32_t  DATAL;                        /*!< (@ 0x00000024) Flash Program Data Low Register                            */
  __IOM uint32_t  PDBCR;                        /*!< (@ 0x00000028) Flash Program Data Buffer Control Register                 */
  __IOM uint32_t  MACR;                         /*!< (@ 0x0000002C) Master Access Control Register                             */
  __IM  uint32_t  ABSSR;                        /*!< (@ 0x00000030) A/B Swap Status Register                                   */
  __IOM uint32_t  DBGPR;                        /*!< (@ 0x00000034) Debug Protection Status Register0                          */
  __IOM uint32_t  DBGKEY0;                      /*!< (@ 0x00000038) Flash Debug Authentication Key Register0                   */
  __IOM uint32_t  DBGKEY1;                      /*!< (@ 0x0000003C) Flash Debug Authentication Key Register1                   */
  __IOM uint32_t  DBGKEY2;                      /*!< (@ 0x00000040) Flash Debug Authentication Key Register2                   */
  __IOM uint32_t  DBGKEY3;                      /*!< (@ 0x00000044) Flash Debug Authentication Key Register3                   */
  __IOM uint32_t  DBGKEY4;                      /*!< (@ 0x00000048) Flash Debug Authentication Key Register4                   */
  __IOM uint32_t  DBGKEY5;                      /*!< (@ 0x0000004C) Flash Debug Authentication Key Register5                   */
  __IOM uint32_t  DBGKEY6;                      /*!< (@ 0x00000050) Flash Debug Authentication Key Register6                   */
  __IOM uint32_t  DBGKEY7;                      /*!< (@ 0x00000054) Flash Debug Authentication Key Register7                   */
  __IOM uint32_t  P0WPR0;                       /*!< (@ 0x00000058) Program Flash Block 0 Write Protection Register0           */
  __IOM uint32_t  P0WPR1;                       /*!< (@ 0x0000005C) Program Flash Block 0 Write Protection Register1           */
  __IOM uint32_t  P0WPR2;                       /*!< (@ 0x00000060) Program Flash Block 0 Write Protection Register2           */
  __IOM uint32_t  P0WPR3;                       /*!< (@ 0x00000064) Program Flash Block 0 Write Protection Register3           */
  __IOM uint32_t  P0WPR4;                       /*!< (@ 0x00000068) Program Flash Block 0 Write Protection Register4           */
  __IOM uint32_t  P0WPR5;                       /*!< (@ 0x0000006C) Program Flash Block 0 Write Protection Register5           */
  __IOM uint32_t  P0WPR6;                       /*!< (@ 0x00000070) Program Flash Block 0 Write Protection Register6           */
  __IOM uint32_t  P0WPR7;                       /*!< (@ 0x00000074) Program Flash Block 0 Write Protection Register7           */
  __IOM uint32_t  P1WPR0;                       /*!< (@ 0x00000078) Program Flash Block 1 Write Protection Register0           */
  __IOM uint32_t  P1WPR1;                       /*!< (@ 0x0000007C) Program Flash Block 1 Write Protection Register1           */
  __IOM uint32_t  P1WPR2;                       /*!< (@ 0x00000080) Program Flash Block 1 Write Protection Register2           */
  __IOM uint32_t  P1WPR3;                       /*!< (@ 0x00000084) Program Flash Block 1 Write Protection Register3           */
  __IOM uint32_t  P1WPR4;                       /*!< (@ 0x00000088) Program Flash Block 1 Write Protection Register4           */
  __IOM uint32_t  P1WPR5;                       /*!< (@ 0x0000008C) Program Flash Block 1 Write Protection Register5           */
  __IOM uint32_t  P1WPR6;                       /*!< (@ 0x00000090) Program Flash Block 1 Write Protection Register6           */
  __IOM uint32_t  P1WPR7;                       /*!< (@ 0x00000094) Program Flash Block 1 Write Protection Register7           */
  __IOM uint32_t  DWPR0;                        /*!< (@ 0x00000098) Data Flash Write Protection Register0                      */
  __IOM uint32_t  DWPR1;                        /*!< (@ 0x0000009C) Data Flash Write Protection Register1                      */
  __IOM uint32_t  DWPR2;                        /*!< (@ 0x000000A0) Data Flash Write Protection Register2                      */
  __IOM uint32_t  DWPR3;                        /*!< (@ 0x000000A4) Data Flash Write Protection Register3                      */
  __IM  uint32_t  UUID0;                        /*!< (@ 0x000000A8) Chip UUID Register0                                        */
  __IM  uint32_t  UUID1;                        /*!< (@ 0x000000AC) Chip UUID Register1                                        */
  __IM  uint32_t  UUID2;                        /*!< (@ 0x000000B0) Chip UUID Register2                                        */
  __IM  uint32_t  UUID3;                        /*!< (@ 0x000000B4) Chip UUID Register3                                        */
  __IM  uint32_t  CMNR;                         /*!< (@ 0x000000B8) Chip Model Name Register                                   */
  __IM  uint32_t  CMIR;                         /*!< (@ 0x000000BC) Chip Memory Information Register                           */
  __IM  uint32_t  CPIR;                         /*!< (@ 0x000000C0) Chip Pin Information Register                              */
} FLASH_Type;                                   /*!< Size = 196 (0xc4)                                                         */


/* =========================================================================================================================== */
/* ================                                           I2C                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief The I2C Memory Map/Register Definition. (I2C)
  */

typedef struct {                                /*!< (@ 0x40017000) I2C Structure                                             */
  __IOM uint32_t  BCR;                          /*!< (@ 0x00000000) Baudrate Control Register                                  */
  __IOM uint32_t  SADDR;                        /*!< (@ 0x00000004) Slave Address Register                                     */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) I2C Control Register                                       */
  __IOM uint32_t  ICR;                          /*!< (@ 0x0000000C) Interrupt Control Register                                 */
  __IOM uint32_t  SAMC;                         /*!< (@ 0x00000010) I2C Slave Address Match control                            */
  __IOM uint32_t  DER;                          /*!< (@ 0x00000014) DMA Enable Register                                        */
  __IOM uint32_t  LTDR;                         /*!< (@ 0x00000018) Low Timeout Detect Register                                */
  __IOM uint32_t  DFCR;                         /*!< (@ 0x0000001C) Deglitch Filter Control Register                           */
  __IOM uint32_t  MCMDR;                        /*!< (@ 0x00000020) Master Command Register                                    */
  __IOM uint32_t  SR0;                          /*!< (@ 0x00000024) I2C Status Register                                        */
  __IM  uint32_t  SR1;                          /*!< (@ 0x00000028) I2C Status Register                                        */
  __IOM uint32_t  DATA;                         /*!< (@ 0x0000002C) Data Degister                                              */
} I2C_Type;                                     /*!< Size = 48 (0x30)                                                          */


/* =========================================================================================================================== */
/* ================                                          TIMER                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Genenal Timer Module (TIMER)
  */

typedef struct {                                /*!< (@ 0x40009000) TIMER Structure                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */
  __IOM uint32_t  PSCR;                         /*!< (@ 0x00000004) Prescaler Register                                         */
  __IOM uint32_t  CMPR;                         /*!< (@ 0x00000008) Compare Register                                           */
  __IOM uint32_t  CNTR;                         /*!< (@ 0x0000000C) Counter Register                                           */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) Status Register                                            */
} TIMER_Type;                                   /*!< Size = 20 (0x14)                                                          */


/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial Peripheral Interface Module (SPI)
  */

typedef struct {                                /*!< (@ 0x40014000) SPI Structure                                              */
  __IOM uint32_t  CFGR;                         /*!< (@ 0x00000000) Configuration Register                                     */
  __IOM uint32_t  CSCFGR;                       /*!< (@ 0x00000004) Chip Select Configuration Register                         */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) Control Register                                           */
  __IOM uint32_t  IER;                          /*!< (@ 0x0000000C) Interrupt Enable Register                                  */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) Status Register                                            */
  __IOM uint32_t  DR;                           /*!< (@ 0x00000014) Data Register                                              */
} SPI_Type;                                     /*!< Size = 24 (0x18)                                                          */


/* =========================================================================================================================== */
/* ================                                           CMP0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Comparator (CMP), Digital-to-Analog Converter (DAC) (CMP)
  */

typedef struct {                                /*!< (@ 0x40006000) CMP Structure                                              */
  __IOM uint32_t  C0;                           /*!< (@ 0x00000000) CMP Control Register 0                                     */
  __IOM uint32_t  C1;                           /*!< (@ 0x00000004) CMP Control Register 1                                     */
  __IOM uint32_t  C2;                           /*!< (@ 0x00000008) CMP Control Register 2                                     */
  __IOM uint32_t  C3;                           /*!< (@ 0x0000000C) CMP Control Register 3                                     */
  __IOM uint32_t  C4;                           /*!< (@ 0x00000010) CMP Control Register 4                                     */
  __IOM uint32_t  C5;                           /*!< (@ 0x00000014) CMP Control Register 5                                     */
  __IOM uint32_t  C6;                           /*!< (@ 0x00000018) CMP Control Register 6                                     */
  __IM  uint32_t  DR;                           /*!< (@ 0x0000001C) CMP Data Register                                          */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000020) CMP Status Register                                        */
} CMP_Type;                                     /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                            PMC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Power Management Controller (PMC)
  */

typedef struct {                                /*!< (@ 0x40002000) PMC Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */
  __IOM uint32_t  PWE;                          /*!< (@ 0x00000004) Peripheral Wakeup Enable Register                          */
} PMC_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */
/** PORT - Size of Registers Arrays */
#define PORT_PIN_COUNT      32U

/**
  * @brief General Purpose Input/Output (GPIO)
  */
typedef struct {                                /*!< (@ 0x40084000) GPIOA Structure                                            */
  __IOM uint32_t  PCR[PORT_PIN_COUNT];          /*!< (@ 0x00000000) Pin Control Register                                       */
  __IOM uint32_t  ODR;                          /*!< (@ 0x00000080) Output Data Register                                       */
  __IOM uint32_t  OSR;                          /*!< (@ 0x00000084) Output Set Register                                        */
  __IOM uint32_t  ORR;                          /*!< (@ 0x00000088) Output Reset Register                                      */
  __IOM uint32_t  OTR;                          /*!< (@ 0x0000008C) Output Toggle Register                                     */
  __IOM uint32_t  IDR;                          /*!< (@ 0x00000090) Input Data Register                                        */
  __IOM uint32_t  IRQF;                         /*!< (@ 0x00000094) Interrupt Flag Register                                    */
  __IOM uint32_t  DFL;                          /*!< (@ 0x00000098) Digital Filter Length                                      */
  __IOM uint32_t  LPDFC;                        /*!< (@ 0x0000009C) Digital Filter Configure In Lowpower Mode                  */
} GPIO_Type;                                    /*!< Size = 160 (0xa0)                                                         */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Cyclic Redundancy Check (CRC)
  */

typedef struct {                                /*!< (@ 0x40082000) CRC Structure                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) CRC Control register                                       */
  union {
    __IOM uint32_t POLY;                        /*!< (@ 0x00000004) CRC Polynomial register                                    */
    struct {
      __IOM uint16_t LOW;                       /**< POLY LOW register., offset: 0x0                                           */
      __IOM uint16_t HIGH;                      /**< POLY HIGH register., offset: 0x2                                          */
    } POLY_16;
  } POLYu;
  union {
    __IOM uint32_t SEED;                        /*!< (@ 0x00000008) CRC Seed register                                          */
    struct {
      __IOM uint16_t LOW;                       /**< SEED LOW register., offset: 0x0                                           */
      __IOM uint16_t HIGH;                      /**< SEED HIGH register., offset: 0x2                                          */
    } SEED_16;
  } SEEDu;
  union {
    __IOM uint32_t DATA;                        /*!< (@ 0x0000000C) CRC Data register                                          */
    struct {
      __IOM uint16_t LOW;                       /**< DATA LOW register., offset: 0x0                                           */
      __IOM uint16_t HIGH;                      /**< DATA HIGH register., offset: 0x2                                          */
    } DATA_16;
    struct {
      __IOM uint8_t LL;                         /**< DATALL register., offset: 0x0                                             */
      __IOM uint8_t LU;                         /**< DATALU register., offset: 0x1                                             */
      __IOM uint8_t HL;                         /**< DATAHL register., offset: 0x2                                             */
      __IOM uint8_t HU;                         /**< DATAHU register., offset: 0x3                                             */
    } DATA_8;
  } DATAu;
} CRC_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                           CAN0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Controller Area Network (CAN)
  */

typedef struct {                                /*!< (@ 0x40011000) CAN0 Structure                                             */
  __IM  uint32_t  RBUFF[20];                    /*!< (@ 0x00000000) CAN receive buffer register                                */
  __IOM uint32_t  TBUFF[18];                    /*!< (@ 0x00000050) CAN transmit buffer register                               */
  __IM  uint32_t  TTS[2];                       /*!< (@ 0x00000098) CAN transmissiom time stamp register                       */
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x000000A0) Config state and transmit/receive control register
                                                                    0                                                          */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x000000A4) CAN interrupt enable/disable and flag control
                                                                    register 1                                                 */
  __IOM uint32_t  SBITRATE;                     /*!< (@ 0x000000A8) Normat CAN baudrate configuration register                 */
  __IOM uint32_t  FBITRATE;                     /*!< (@ 0x000000AC) FAST CAN(CAN_FD) baudrate configuration register           */
  __IOM uint32_t  ERRINFO;                      /*!< (@ 0x000000B0) CAN error type and transmit/receive error conunter
                                                                    register                                                   */
  __IOM uint32_t  ACFCTRL0;                     /*!< (@ 0x000000B4) Acceptance Filter Control Register                        */
  __IOM uint32_t  ACFCTRL1;                     /*!< (@ 0x000000B4) Acceptance Filter Control Register                        */
  __IOM uint32_t  ACF;                          /*!< (@ 0x000000B8) Acceptance Code Register                                   */
  __IM  uint32_t  VERSION;                      /*!< (@ 0x000000BC) Version Information Register 0                             */
} CAN_Type;                                     /*!< Size = 192 (0xc0)                                                         */

/* =========================================================================================================================== */
/* ================                                            HSM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Hardware Security Module (HSM)
  */

typedef struct {                                /*!< (@ 0x40084000) HSM Structure                                              */
  __IOM uint32_t  ESR;                          /*!< (@ 0x00000000) HSM Error Status                                           */
  __IOM uint32_t  EIE;                          /*!< (@ 0x00000004) HSM Error Interrupt Enable                                 */
  __IM  uint32_t  FWSTA0;                       /*!< (@ 0x00000008) HSM FW STATUS0                                             */
  __IM  uint32_t  FWSTA1;                       /*!< (@ 0x0000000C) HSM FW STATUS1                                             */
  __IM  uint32_t  DBGSTA;                       /*!< (@ 0x00000010) DEBUG STATUS                                               */
} HSM_Type;                                     /*!< Size = 20 (0x14)                                                          */


/* =========================================================================================================================== */
/* ================                                            MBOX                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Mail Box (MBOX)
  */

typedef struct {                                  /*!< (@ 0x40083000) MB Structure                                               */
    __IOM uint32_t  S2H_INFO[32];                 /*!< (@ 0x00000000) Soc to HSM information Register0                           */
    __IM  uint32_t  H2S_INFO[32];                 /*!< (@ 0x00000080) HSM to Soc information Register0                           */
    __IOM uint32_t  S2H_NOTE;                     /*!< (@ 0x00000100) Soc to HSM NOTE Register                                   */
    __IOM uint32_t  H2S_NOTE;                     /*!< (@ 0x00000104) HSM to Soc NOTE Register                                   */
    __IM  uint32_t  RESERVED2[2];
    __IOM uint32_t  S2H_SOC_INT;                  /*!< (@ 0x00000110) Soc to HSM Soc Interrupt Register                          */
    __IOM uint32_t  S2H_SOC_INT_EN;               /*!< (@ 0x00000114) Soc to HSM Soc Interrupt Enable Register                   */
    __IM  uint32_t  S2H_HSM_INT;                  /*!< (@ 0x00000118) Soc to HSM HSM Interrupt Register                          */
    __IM  uint32_t  S2H_HSM_INT_EN;               /*!< (@ 0x0000011C) Soc to HSM HSM Interrupt Enable Register                   */
    __IOM uint32_t  H2S_SOC_INT;                  /*!< (@ 0x00000120) HSM to SOC Soc Interrupt Register                          */
    __IOM uint32_t  H2S_SOC_INT_EN;               /*!< (@ 0x00000124) HSM to Soc Soc Interrupt Enable Register                   */
    __IM  uint32_t  H2S_HSM_INT;                  /*!< (@ 0x00000128) HSM to SOC HSM Interrupt Register                          */
    __IM  uint32_t  H2S_HSM_INT_EN;               /*!< (@ 0x0000012C) HSM to SOC HSM Interrupt Enable Register                   */
    __IM  uint32_t  RESERVED3[52];
    __IM  uint32_t  STATUS0;                      /*!< (@ 0x00000200) HSM STATUS0 Register                                       */
    __IM  uint32_t  STATUS1;                      /*!< (@ 0x00000204) HSM STATUS1 Register                                       */
} MBOX_Type;                                      /*!< Size = 520 (0x208)                                                        */

/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */
#define RESET_BASE                  0x40000000UL
#define CLOCK_BASE                  0x40001000UL
#define PMC_BASE                    0x40002000UL
#define CMP0_BASE                   0x40006000UL
#define ICM_BASE                    0x40007000UL
#define RTC_BASE                    0x40008000UL
#define WDG_BASE                    0x40009000UL
#define TIMER0_BASE                 0x4000A000UL
#define TIMER1_BASE                 0x4000B000UL
#define TIMER2_BASE                 0x4000C000UL
#define TIMER3_BASE                 0x4000D000UL
#define GPIOA_BASE                  0x4000E000UL
#define GPIOB_BASE                  0x4000E200UL
#define GPIOC_BASE                  0x4000E400UL
#define GPIOD_BASE                  0x4000E600UL
#define GPIOE_BASE                  0x4000E800UL
#define FLASH_BASE                  0x40010000UL
#define CAN0_BASE                   0x40011000UL
#define CAN1_BASE                   0x40012000UL
#define CAN2_BASE                   0x40013000UL
#define I2C0_BASE                   0x40017000UL
#define I2C1_BASE                   0x40018000UL
#define SPI0_BASE                   0x40019000UL
#define SPI1_BASE                   0x4001A000UL
#define SPI2_BASE                   0x4001B000UL
#define SPI3_BASE                   0x4001C000UL
#define UART0_BASE                  0x40020000UL
#define UART1_BASE                  0x40021000UL
#define UART2_BASE                  0x40022000UL
#define UART3_BASE                  0x40023000UL
#define IPWM0_BASE                  0x40026000UL
#define IPWM1_BASE                  0x40027000UL
#define SPWM0_BASE                  0x40028000UL
#define SPWM1_BASE                  0x40029000UL
#define SPWM2_BASE                  0x4002A000UL
#define ADC0_BASE                   0x4002C000UL
#define ADC1_BASE                   0x4002D000UL
#define DMA_BASE                    0x40080000UL
#define DMA_CH0_BASE                0x40080020UL
#define DMA_CH1_BASE                0x40080040UL
#define DMA_CH2_BASE                0x40080060UL
#define DMA_CH3_BASE                0x40080080UL
#define DMA_CH4_BASE                0x400800A0UL
#define DMA_CH5_BASE                0x400800C0UL
#define DMA_CH6_BASE                0x400800E0UL
#define DMA_CH7_BASE                0x40080100UL
#define CRC_BASE                    0x40081000UL
#define ERM_BASE                    0x40082000UL
#define MBOX_BASE                   0x40083000UL
#define HSM_BASE                    0x40084000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */

/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define RESET                       ((RESET_Type*)             RESET_BASE)
#define CLOCK                       ((CLOCK_Type*)             CLOCK_BASE)
#define PMC                         ((PMC_Type*)               PMC_BASE)
#define ADC0                        ((ADC_Type*)               ADC0_BASE)
#define ADC1                        ((ADC_Type*)               ADC1_BASE)
#define CMP0                        ((CMP_Type*)               CMP0_BASE)
#define ICM                         ((ICM_Type*)               ICM_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define WDG                         ((WDG_Type*)               WDG_BASE)
#define FLASH                       ((FLASH_Type*)             FLASH_BASE)
#define CAN0                        ((CAN_Type*)               CAN0_BASE)
#define CAN1                        ((CAN_Type*)               CAN1_BASE)
#define CAN2                        ((CAN_Type*)               CAN2_BASE)
#define I2C0                        ((I2C_Type*)               I2C0_BASE)
#define I2C1                        ((I2C_Type*)               I2C1_BASE)
#define TIMER0                      ((TIMER_Type*)             TIMER0_BASE)
#define TIMER1                      ((TIMER_Type*)             TIMER1_BASE)
#define TIMER2                      ((TIMER_Type*)             TIMER2_BASE)
#define TIMER3                      ((TIMER_Type*)             TIMER3_BASE)
#define SPI0                        ((SPI_Type*)               SPI0_BASE)
#define SPI1                        ((SPI_Type*)               SPI1_BASE)
#define SPI2                        ((SPI_Type*)               SPI2_BASE)
#define SPI3                        ((SPI_Type*)               SPI3_BASE)
#define UART0                       ((UART_Type *)             UART0_BASE)
#define UART1                       ((UART_Type *)             UART1_BASE)
#define UART2                       ((UART_Type *)             UART2_BASE)
#define UART3                       ((UART_Type *)             UART3_BASE)
#define DMA                         ((DMA_Type*)               DMA_BASE)
#define DMA_CH0                     ((DMA_CH_Type *)           DMA_CH0_BASE)
#define DMA_CH1                     ((DMA_CH_Type *)           DMA_CH1_BASE)
#define DMA_CH2                     ((DMA_CH_Type *)           DMA_CH2_BASE)
#define DMA_CH3                     ((DMA_CH_Type *)           DMA_CH3_BASE)
#define DMA_CH4                     ((DMA_CH_Type *)           DMA_CH4_BASE)
#define DMA_CH5                     ((DMA_CH_Type *)           DMA_CH5_BASE)
#define DMA_CH6                     ((DMA_CH_Type *)           DMA_CH6_BASE)
#define DMA_CH7                     ((DMA_CH_Type *)           DMA_CH7_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define ERM                         ((ERM_Type*)               ERM_BASE)
#define GPIOA                       ((GPIO_Type*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_Type*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_Type*)              GPIOC_BASE)
#define GPIOD                       ((GPIO_Type*)              GPIOD_BASE)
#define GPIOE                       ((GPIO_Type*)              GPIOE_BASE)
#define IPWM0                       ((IPWM_Type*)              IPWM0_BASE)
#define IPWM1                       ((IPWM_Type*)              IPWM1_BASE)
#define SPWM0                       ((SPWM_Type*)              SPWM0_BASE)
#define SPWM1                       ((SPWM_Type*)              SPWM1_BASE)
#define SPWM2                       ((SPWM_Type*)              SPWM2_BASE)
#define MBOX                        ((MBOX_Type*)              MBOX_BASE)
#define HSM                         ((HSM_Type*)               HSM_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */

/** @addtogroup PosMask_peripherals
  * @{
  */

/* =========================================================================================================================== */
/* ================                                           RESET                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define RESET_CR_EPREN_Pos                (2UL)                     /*!< EPREN (Bit 2)                                         */
#define RESET_CR_EPREN_Msk                (0x4UL)                   /*!< EPREN (Bitfield-Mask: 0x01)                           */
#define RESET_CR_WDGEN_Pos                (3UL)                     /*!< WDGEN (Bit 3)                                         */
#define RESET_CR_WDGEN_Msk                (0x8UL)                   /*!< WDGEN (Bitfield-Mask: 0x01)                           */
#define RESET_CR_LOCEN_Pos                (4UL)                     /*!< LOCEN (Bit 4)                                         */
#define RESET_CR_LOCEN_Msk                (0x10UL)                  /*!< LOCEN (Bitfield-Mask: 0x01)                           */
#define RESET_CR_LOLEN_Pos                (5UL)                     /*!< LOLEN (Bit 5)                                         */
#define RESET_CR_LOLEN_Msk                (0x20UL)                  /*!< LOLEN (Bitfield-Mask: 0x01)                           */
#define RESET_CR_SWEN_Pos                 (6UL)                     /*!< SWEN (Bit 6)                                          */
#define RESET_CR_SWEN_Msk                 (0x40UL)                  /*!< SWEN (Bitfield-Mask: 0x01)                            */
#define RESET_CR_LOCKUPEN_Pos             (7UL)                     /*!< LOCKUPEN (Bit 7)                                      */
#define RESET_CR_LOCKUPEN_Msk             (0x80UL)                  /*!< LOCKUPEN (Bitfield-Mask: 0x01)                        */
#define RESET_CR_ACKERREN_Pos             (8UL)                     /*!< ACKERREN (Bit 8)                                      */
#define RESET_CR_ACKERREN_Msk             (0x100UL)                 /*!< ACKERREN (Bitfield-Mask: 0x01)                        */
#define RESET_CR_HSMERREN_Pos             (9UL)                     /*!< HSMERREN (Bit 9)                                      */
#define RESET_CR_HSMERREN_Msk             (0x200UL)                 /*!< HSMERREN (Bitfield-Mask: 0x01)                        */
/* ==========================================================  FCR  ========================================================== */
#define RESET_FCR_FLTEN_Pos               (0UL)                     /*!< FLTEN (Bit 0)                                         */
#define RESET_FCR_FLTEN_Msk               (0x1UL)                   /*!< FLTEN (Bitfield-Mask: 0x01)                           */
#define RESET_FCR_FLTVAL_Pos              (4UL)                     /*!< FLTVAL (Bit 4)                                        */
#define RESET_FCR_FLTVAL_Msk              (0x1f0UL)                 /*!< FLTVAL (Bitfield-Mask: 0x1f)                          */
/* ==========================================================  SR  =========================================================== */
#define RESET_SR_PORF_Pos                 (0UL)                     /*!< PORF (Bit 0)                                          */
#define RESET_SR_PORF_Msk                 (0x1UL)                   /*!< PORF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_LVRF_Pos                 (1UL)                     /*!< LVRF (Bit 1)                                          */
#define RESET_SR_LVRF_Msk                 (0x2UL)                   /*!< LVRF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_EPRF_Pos                 (2UL)                     /*!< EPRF (Bit 2)                                          */
#define RESET_SR_EPRF_Msk                 (0x4UL)                   /*!< EPRF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_WDGF_Pos                 (3UL)                     /*!< WDGF (Bit 3)                                          */
#define RESET_SR_WDGF_Msk                 (0x8UL)                   /*!< WDGF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_LOCF_Pos                 (4UL)                     /*!< LOCF (Bit 4)                                          */
#define RESET_SR_LOCF_Msk                 (0x10UL)                  /*!< LOCF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_LOLF_Pos                 (5UL)                     /*!< LOLF (Bit 5)                                          */
#define RESET_SR_LOLF_Msk                 (0x20UL)                  /*!< LOLF (Bitfield-Mask: 0x01)                            */
#define RESET_SR_SWF_Pos                  (6UL)                     /*!< SWF (Bit 6)                                           */
#define RESET_SR_SWF_Msk                  (0x40UL)                  /*!< SWF (Bitfield-Mask: 0x01)                             */
#define RESET_SR_LOCKUPF_Pos              (7UL)                     /*!< LOCKUPF (Bit 7)                                       */
#define RESET_SR_LOCKUPF_Msk              (0x80UL)                  /*!< LOCKUPF (Bitfield-Mask: 0x01)                         */
#define RESET_SR_ACKERRF_Pos              (8UL)                     /*!< ACKERRF (Bit 8)                                       */
#define RESET_SR_ACKERRF_Msk              (0x100UL)                 /*!< ACKERRF (Bitfield-Mask: 0x01)                         */
#define RESET_SR_HSMERRF_Pos              (9UL)                     /*!< HSMERRF (Bit 9)                                       */
#define RESET_SR_HSMERRF_Msk              (0x200UL)                 /*!< HSMERRF (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                           CLOCK                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define CLOCK_CR_HSISTOPEN_Pos            (0UL)                     /*!< HSISTOPEN (Bit 0)                                     */
#define CLOCK_CR_HSISTOPEN_Msk            (0x1UL)                   /*!< HSISTOPEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_CR_CORECLKEN_Pos            (1UL)                     /*!< CORECLKEN (Bit 1)                                     */
#define CLOCK_CR_CORECLKEN_Msk            (0x2UL)                   /*!< CORECLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_CR_SYSCLKSRC_Pos            (4UL)                     /*!< SYSCLKSRC (Bit 4)                                     */
#define CLOCK_CR_SYSCLKSRC_Msk            (0x30UL)                  /*!< SYSCLKSRC (Bitfield-Mask: 0x03)                       */
#define CLOCK_CR_PERI0PVAL_Pos            (6UL)                     /*!< PERI0PVAL (Bit 6)                                     */
#define CLOCK_CR_PERI0PVAL_Msk            (0xc0UL)                  /*!< PERI0PVAL (Bitfield-Mask: 0x03)                       */
#define CLOCK_CR_AHBPVAL_Pos              (8UL)                     /*!< AHBPVAL (Bit 8)                                       */
#define CLOCK_CR_AHBPVAL_Msk              (0x300UL)                 /*!< AHBPVAL (Bitfield-Mask: 0x03)                         */
#define CLOCK_CR_PERI1PVAL_Pos            (10UL)                    /*!< PERI1PVAL (Bit 10)                                    */
#define CLOCK_CR_PERI1PVAL_Msk            (0xc00UL)                 /*!< PERI1PVAL (Bitfield-Mask: 0x03)                       */
#define CLOCK_CR_APBPVAL_Pos              (12UL)                    /*!< APBPVAL (Bit 12)                                      */
#define CLOCK_CR_APBPVAL_Msk              (0x3000UL)                /*!< APBPVAL (Bitfield-Mask: 0x03)                         */
#define CLOCK_CR_LOCFS_Pos                (30UL)                    /*!< LOCFS (Bit 30)                                        */
#define CLOCK_CR_LOCFS_Msk                (0x40000000UL)            /*!< LOCFS (Bitfield-Mask: 0x01)                           */
#define CLOCK_CR_LOLFS_Pos                (31UL)                    /*!< LOLFS (Bit 31)                                        */
#define CLOCK_CR_LOLFS_Msk                (0x80000000UL)            /*!< LOLFS (Bitfield-Mask: 0x01)                           */
/* ========================================================  XOSCCR  ========================================================= */
#define CLOCK_XOSCCR_EN_Pos               (0UL)                     /*!< EN (Bit 0)                                            */
#define CLOCK_XOSCCR_EN_Msk               (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define CLOCK_XOSCCR_BYPEN_Pos            (1UL)                     /*!< BYPEN (Bit 1)                                         */
#define CLOCK_XOSCCR_BYPEN_Msk            (0x2UL)                   /*!< BYPEN (Bitfield-Mask: 0x01)                           */
#define CLOCK_XOSCCR_IBS_Pos              (2UL)                     /*!< IBS (Bit 2)                                           */
#define CLOCK_XOSCCR_IBS_Msk              (0x4UL)                   /*!< IBS (Bitfield-Mask: 0x01)                             */
#define CLOCK_XOSCCR_MONEN_Pos            (8UL)                     /*!< MONEN (Bit 8)                                         */
#define CLOCK_XOSCCR_MONEN_Msk            (0x100UL)                 /*!< MONEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  PLLCR  ========================================================= */
#define CLOCK_PLLCR_EN_Pos                (0UL)                     /*!< EN (Bit 0)                                            */
#define CLOCK_PLLCR_EN_Msk                (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
#define CLOCK_PLLCR_REFSEL_Pos            (1UL)                     /*!< REFSEL (Bit 1)                                        */
#define CLOCK_PLLCR_REFSEL_Msk            (0x2UL)                   /*!< REFSEL (Bitfield-Mask: 0x01)                          */
#define CLOCK_PLLCR_LOCKMONEN_Pos         (2UL)                     /*!< LOCKMONEN (Bit 2)                                     */
#define CLOCK_PLLCR_LOCKMONEN_Msk         (0x4UL)                   /*!< LOCKMONEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_PLLCR_LOCKEN_Pos            (3UL)                     /*!< LOCKEN (Bit 3)                                        */
#define CLOCK_PLLCR_LOCKEN_Msk            (0x8UL)                   /*!< LOCKEN (Bitfield-Mask: 0x01)                          */
#define CLOCK_PLLCR_PREDIV_Pos            (4UL)                     /*!< PREDIV (Bit 4)                                        */
#define CLOCK_PLLCR_PREDIV_Msk            (0x3f0UL)                 /*!< PREDIV (Bitfield-Mask: 0x3f)                          */
#define CLOCK_PLLCR_FBDIV_Pos             (10UL)                    /*!< FBDIV (Bit 10)                                        */
#define CLOCK_PLLCR_FBDIV_Msk             (0x3ffc00UL)              /*!< FBDIV (Bitfield-Mask: 0xfff)                          */
#define CLOCK_PLLCR_POSTDIV1_Pos          (22UL)                    /*!< POSTDIV1 (Bit 22)                                     */
#define CLOCK_PLLCR_POSTDIV1_Msk          (0x1c00000UL)             /*!< POSTDIV1 (Bitfield-Mask: 0x07)                        */
#define CLOCK_PLLCR_POSTDIV2_Pos          (25UL)                    /*!< POSTDIV2 (Bit 25)                                     */
#define CLOCK_PLLCR_POSTDIV2_Msk          (0x6000000UL)             /*!< POSTDIV2 (Bitfield-Mask: 0x03)                        */
#define CLOCK_PLLCR_LFR_Pos               (27UL)                    /*!< LFR (Bit 27)                                          */
#define CLOCK_PLLCR_LFR_Msk               (0x8000000UL)             /*!< LFR (Bitfield-Mask: 0x01)                             */
#define CLOCK_PLLCR_ICP_Pos               (28UL)                    /*!< ICP (Bit 28)                                          */
#define CLOCK_PLLCR_ICP_Msk               (0xf0000000UL)            /*!< ICP (Bitfield-Mask: 0x0f)                             */
/* ==========================================================  SR  =========================================================== */
#define CLOCK_SR_LOLF_Pos                 (0UL)                     /*!< LOLF (Bit 0)                                          */
#define CLOCK_SR_LOLF_Msk                 (0x1UL)                   /*!< LOLF (Bitfield-Mask: 0x01)                            */
#define CLOCK_SR_LOCF_Pos                 (1UL)                     /*!< LOCF (Bit 1)                                          */
#define CLOCK_SR_LOCF_Msk                 (0x2UL)                   /*!< LOCF (Bitfield-Mask: 0x01)                            */
#define CLOCK_SR_PLLLKDF_Pos              (2UL)                     /*!< PLLLKDF (Bit 2)                                       */
#define CLOCK_SR_PLLLKDF_Msk              (0x4UL)                   /*!< PLLLKDF (Bitfield-Mask: 0x01)                         */
#define CLOCK_SR_HSERDYF_Pos              (3UL)                     /*!< HSERDYF (Bit 3)                                       */
#define CLOCK_SR_HSERDYF_Msk              (0x8UL)                   /*!< HSERDYF (Bitfield-Mask: 0x01)                         */
#define CLOCK_SR_PLLRDYF_Pos              (4UL)                     /*!< PLLRDYF (Bit 4)                                       */
#define CLOCK_SR_PLLRDYF_Msk              (0x10UL)                  /*!< PLLRDYF (Bitfield-Mask: 0x01)                         */
/* ========================================================  AHBPCCR  ======================================================== */
#define CLOCK_AHBPCCR_DMACLKEN_Pos        (0UL)                     /*!< DMACLKEN (Bit 0)                                      */
#define CLOCK_AHBPCCR_DMACLKEN_Msk        (0x1UL)                   /*!< DMACLKEN (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPCCR_CRCCLKEN_Pos        (2UL)                     /*!< CRCCLKEN (Bit 2)                                      */
#define CLOCK_AHBPCCR_CRCCLKEN_Msk        (0x4UL)                   /*!< CRCCLKEN (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPCCR_SPWM0CLKEN_Pos      (4UL)                     /*!< SPWM0CLKEN (Bit 4)                                    */
#define CLOCK_AHBPCCR_SPWM0CLKEN_Msk      (0x10UL)                  /*!< SPWM0CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_AHBPCCR_SPWM1CLKEN_Pos      (5UL)                     /*!< SPWM1CLKEN (Bit 5)                                    */
#define CLOCK_AHBPCCR_SPWM1CLKEN_Msk      (0x20UL)                  /*!< SPWM1CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_AHBPCCR_SPWM2CLKEN_Pos      (6UL)                     /*!< SPWM2CLKEN (Bit 6)                                    */
#define CLOCK_AHBPCCR_SPWM2CLKEN_Msk      (0x40UL)                  /*!< SPWM2CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_AHBPCCR_IPWM0CLKEN_Pos      (8UL)                     /*!< IPWM0CLKEN (Bit 8)                                    */
#define CLOCK_AHBPCCR_IPWM0CLKEN_Msk      (0x100UL)                 /*!< IPWM0CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_AHBPCCR_IPWM1CLKEN_Pos      (9UL)                     /*!< IPWM1CLKEN (Bit 9)                                    */
#define CLOCK_AHBPCCR_IPWM1CLKEN_Msk      (0x200UL)                 /*!< IPWM1CLKEN (Bitfield-Mask: 0x01)                      */
/* ========================================================  APBPCCR  ======================================================== */
#define CLOCK_APBPCCR_I2C0CLKEN_Pos       (0UL)                     /*!< I2C0CLKEN (Bit 0)                                     */
#define CLOCK_APBPCCR_I2C0CLKEN_Msk       (0x1UL)                   /*!< I2C0CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_I2C1CLKEN_Pos       (1UL)                     /*!< I2C1CLKEN (Bit 1)                                     */
#define CLOCK_APBPCCR_I2C1CLKEN_Msk       (0x2UL)                   /*!< I2C1CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_UART0CLKEN_Pos      (2UL)                     /*!< UART0CLKEN (Bit 2)                                    */
#define CLOCK_APBPCCR_UART0CLKEN_Msk      (0x4UL)                   /*!< UART0CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_APBPCCR_UART1CLKEN_Pos      (3UL)                     /*!< UART1CLKEN (Bit 3)                                    */
#define CLOCK_APBPCCR_UART1CLKEN_Msk      (0x8UL)                   /*!< UART1CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_APBPCCR_UART2CLKEN_Pos      (4UL)                     /*!< UART2CLKEN (Bit 4)                                    */
#define CLOCK_APBPCCR_UART2CLKEN_Msk      (0x10UL)                  /*!< UART2CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_APBPCCR_UART3CLKEN_Pos      (5UL)                     /*!< UART3CLKEN (Bit 5)                                    */
#define CLOCK_APBPCCR_UART3CLKEN_Msk      (0x20UL)                  /*!< UART3CLKEN (Bitfield-Mask: 0x01)                      */
#define CLOCK_APBPCCR_SPI0CLKEN_Pos       (7UL)                     /*!< SPI0CLKEN (Bit 7)                                     */
#define CLOCK_APBPCCR_SPI0CLKEN_Msk       (0x80UL)                  /*!< SPI0CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_SPI1CLKEN_Pos       (8UL)                     /*!< SPI1CLKEN (Bit 8)                                     */
#define CLOCK_APBPCCR_SPI1CLKEN_Msk       (0x100UL)                 /*!< SPI1CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_SPI2CLKEN_Pos       (9UL)                     /*!< SPI2CLKEN (Bit 9)                                     */
#define CLOCK_APBPCCR_SPI2CLKEN_Msk       (0x200UL)                 /*!< SPI2CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_SPI3CLKEN_Pos       (10UL)                    /*!< SPI3CLKEN (Bit 10)                                    */
#define CLOCK_APBPCCR_SPI3CLKEN_Msk       (0x400UL)                 /*!< SPI3CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_CAN0CLKEN_Pos       (11UL)                    /*!< CAN0CLKEN (Bit 11)                                    */
#define CLOCK_APBPCCR_CAN0CLKEN_Msk       (0x800UL)                 /*!< CAN0CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_CAN1CLKEN_Pos       (12UL)                    /*!< CAN1CLKEN (Bit 12)                                    */
#define CLOCK_APBPCCR_CAN1CLKEN_Msk       (0x1000UL)                /*!< CAN1CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_CAN2CLKEN_Pos       (13UL)                    /*!< CAN2CLKEN (Bit 13)                                    */
#define CLOCK_APBPCCR_CAN2CLKEN_Msk       (0x2000UL)                /*!< CAN2CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_TIMER0CLKEN_Pos     (14UL)                    /*!< TIMER0CLKEN (Bit 14)                                  */
#define CLOCK_APBPCCR_TIMER0CLKEN_Msk     (0x4000UL)                /*!< TIMER0CLKEN (Bitfield-Mask: 0x01)                     */
#define CLOCK_APBPCCR_TIMER1CLKEN_Pos     (15UL)                    /*!< TIMER1CLKEN (Bit 15)                                  */
#define CLOCK_APBPCCR_TIMER1CLKEN_Msk     (0x8000UL)                /*!< TIMER1CLKEN (Bitfield-Mask: 0x01)                     */
#define CLOCK_APBPCCR_TIMER2CLKEN_Pos     (16UL)                    /*!< TIMER2CLKEN (Bit 16)                                  */
#define CLOCK_APBPCCR_TIMER2CLKEN_Msk     (0x10000UL)               /*!< TIMER2CLKEN (Bitfield-Mask: 0x01)                     */
#define CLOCK_APBPCCR_TIMER3CLKEN_Pos     (17UL)                    /*!< TIMER3CLKEN (Bit 17)                                  */
#define CLOCK_APBPCCR_TIMER3CLKEN_Msk     (0x20000UL)               /*!< TIMER3CLKEN (Bitfield-Mask: 0x01)                     */
#define CLOCK_APBPCCR_CMP0CLKEN_Pos       (18UL)                    /*!< CMP0CLKEN (Bit 18)                                    */
#define CLOCK_APBPCCR_CMP0CLKEN_Msk       (0x40000UL)               /*!< CMP0CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_ADC0CLKEN_Pos       (19UL)                    /*!< ADC0CLKEN (Bit 19)                                    */
#define CLOCK_APBPCCR_ADC0CLKEN_Msk       (0x80000UL)               /*!< ADC0CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_ADC1CLKEN_Pos       (20UL)                    /*!< ADC1CLKEN (Bit 20)                                    */
#define CLOCK_APBPCCR_ADC1CLKEN_Msk       (0x100000UL)              /*!< ADC1CLKEN (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPCCR_ICMCLKEN_Pos        (21UL)                    /*!< ICMCLKEN (Bit 21)                                     */
#define CLOCK_APBPCCR_ICMCLKEN_Msk        (0x200000UL)              /*!< ICMCLKEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  AHBPSRR  ======================================================== */
#define CLOCK_AHBPSRR_DMARST_Pos          (0UL)                     /*!< DMARST (Bit 0)                                        */
#define CLOCK_AHBPSRR_DMARST_Msk          (0x1UL)                   /*!< DMARST (Bitfield-Mask: 0x01)                          */
#define CLOCK_AHBPSRR_CRCRST_Pos          (2UL)                     /*!< CRCRST (Bit 2)                                        */
#define CLOCK_AHBPSRR_CRCRST_Msk          (0x4UL)                   /*!< CRCRST (Bitfield-Mask: 0x01)                          */
#define CLOCK_AHBPSRR_SPWM0RST_Pos        (4UL)                     /*!< SPWM0RST (Bit 4)                                      */
#define CLOCK_AHBPSRR_SPWM0RST_Msk        (0x10UL)                  /*!< SPWM0RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPSRR_SPWM1RST_Pos        (5UL)                     /*!< SPWM1RST (Bit 5)                                      */
#define CLOCK_AHBPSRR_SPWM1RST_Msk        (0x20UL)                  /*!< SPWM1RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPSRR_SPWM2RST_Pos        (6UL)                     /*!< SPWM2RST (Bit 6)                                      */
#define CLOCK_AHBPSRR_SPWM2RST_Msk        (0x40UL)                  /*!< SPWM2RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPSRR_IPWM0RST_Pos        (8UL)                     /*!< IPWM0RST (Bit 8)                                      */
#define CLOCK_AHBPSRR_IPWM0RST_Msk        (0x100UL)                 /*!< IPWM0RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_AHBPSRR_IPWM1RST_Pos        (9UL)                     /*!< IPWM1RST (Bit 9)                                      */
#define CLOCK_AHBPSRR_IPWM1RST_Msk        (0x200UL)                 /*!< IPWM1RST (Bitfield-Mask: 0x01)                        */
/* ========================================================  APBPSRR  ======================================================== */
#define CLOCK_APBPSRR_I2C0RST_Pos         (0UL)                     /*!< I2C0RST (Bit 0)                                       */
#define CLOCK_APBPSRR_I2C0RST_Msk         (0x1UL)                   /*!< I2C0RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_I2C1RST_Pos         (1UL)                     /*!< I2C1RST (Bit 1)                                       */
#define CLOCK_APBPSRR_I2C1RST_Msk         (0x2UL)                   /*!< I2C1RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_UART0RST_Pos        (2UL)                     /*!< UART0RST (Bit 2)                                      */
#define CLOCK_APBPSRR_UART0RST_Msk        (0x4UL)                   /*!< UART0RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_APBPSRR_UART1RST_Pos        (3UL)                     /*!< UART1RST (Bit 3)                                      */
#define CLOCK_APBPSRR_UART1RST_Msk        (0x8UL)                   /*!< UART1RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_APBPSRR_UART2RST_Pos        (4UL)                     /*!< UART2RST (Bit 4)                                      */
#define CLOCK_APBPSRR_UART2RST_Msk        (0x10UL)                  /*!< UART2RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_APBPSRR_UART3RST_Pos        (5UL)                     /*!< UART3RST (Bit 5)                                      */
#define CLOCK_APBPSRR_UART3RST_Msk        (0x20UL)                  /*!< UART3RST (Bitfield-Mask: 0x01)                        */
#define CLOCK_APBPSRR_SPI0RST_Pos         (7UL)                     /*!< SPI0RST (Bit 7)                                       */
#define CLOCK_APBPSRR_SPI0RST_Msk         (0x80UL)                  /*!< SPI0RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_SPI1RST_Pos         (8UL)                     /*!< SPI1RST (Bit 8)                                       */
#define CLOCK_APBPSRR_SPI1RST_Msk         (0x100UL)                 /*!< SPI1RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_SPI2RST_Pos         (9UL)                     /*!< SPI2RST (Bit 9)                                       */
#define CLOCK_APBPSRR_SPI2RST_Msk         (0x200UL)                 /*!< SPI2RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_SPI3RST_Pos         (10UL)                    /*!< SPI3RST (Bit 10)                                      */
#define CLOCK_APBPSRR_SPI3RST_Msk         (0x400UL)                 /*!< SPI3RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_CAN0RST_Pos         (11UL)                    /*!< CAN0RST (Bit 11)                                      */
#define CLOCK_APBPSRR_CAN0RST_Msk         (0x800UL)                 /*!< CAN0RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_CAN1RST_Pos         (12UL)                    /*!< CAN1RST (Bit 12)                                      */
#define CLOCK_APBPSRR_CAN1RST_Msk         (0x1000UL)                /*!< CAN1RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_CAN2RST_Pos         (13UL)                    /*!< CAN2RST (Bit 13)                                      */
#define CLOCK_APBPSRR_CAN2RST_Msk         (0x2000UL)                /*!< CAN2RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_TIMER0RST_Pos       (14UL)                    /*!< TIMER0RST (Bit 14)                                    */
#define CLOCK_APBPSRR_TIMER0RST_Msk       (0x4000UL)                /*!< TIMER0RST (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPSRR_TIMER1RST_Pos       (15UL)                    /*!< TIMER1RST (Bit 15)                                    */
#define CLOCK_APBPSRR_TIMER1RST_Msk       (0x8000UL)                /*!< TIMER1RST (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPSRR_TIMER2RST_Pos       (16UL)                    /*!< TIMER2RST (Bit 16)                                    */
#define CLOCK_APBPSRR_TIMER2RST_Msk       (0x10000UL)               /*!< TIMER2RST (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPSRR_TIMER3RST_Pos       (17UL)                    /*!< TIMER3RST (Bit 17)                                    */
#define CLOCK_APBPSRR_TIMER3RST_Msk       (0x20000UL)               /*!< TIMER3RST (Bitfield-Mask: 0x01)                       */
#define CLOCK_APBPSRR_CMP0RST_Pos         (18UL)                    /*!< CMP0RST (Bit 18)                                      */
#define CLOCK_APBPSRR_CMP0RST_Msk         (0x40000UL)               /*!< CMP0RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_ADC0RST_Pos         (19UL)                    /*!< ADC0RST (Bit 19)                                      */
#define CLOCK_APBPSRR_ADC0RST_Msk         (0x80000UL)               /*!< ADC0RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_ADC1RST_Pos         (20UL)                    /*!< ADC1RST (Bit 20)                                      */
#define CLOCK_APBPSRR_ADC1RST_Msk         (0x100000UL)              /*!< ADC1RST (Bitfield-Mask: 0x01)                         */
#define CLOCK_APBPSRR_ICMRST_Pos          (21UL)                    /*!< ICMRST (Bit 21)                                       */
#define CLOCK_APBPSRR_ICMRST_Msk          (0x200000UL)              /*!< ICMRST (Bitfield-Mask: 0x01)                          */
/* =========================================================  PFCSR  ========================================================= */
#define CLOCK_PFCSR_ADC0CLKSEL_Pos        (0UL)                     /*!< ADC0CLKSEL (Bit 0)                                    */
#define CLOCK_PFCSR_ADC0CLKSEL_Msk        (0x3UL)                   /*!< ADC0CLKSEL (Bitfield-Mask: 0x03)                      */
#define CLOCK_PFCSR_ADC1CLKSEL_Pos        (2UL)                     /*!< ADC1CLKSEL (Bit 2)                                    */
#define CLOCK_PFCSR_ADC1CLKSEL_Msk        (0xcUL)                   /*!< ADC1CLKSEL (Bitfield-Mask: 0x03)                      */
#define CLOCK_PFCSR_CAN0CLKSEL_Pos        (4UL)                     /*!< CAN0CLKSEL (Bit 4)                                    */
#define CLOCK_PFCSR_CAN0CLKSEL_Msk        (0x30UL)                  /*!< CAN0CLKSEL (Bitfield-Mask: 0x03)                      */
#define CLOCK_PFCSR_CAN1CLKSEL_Pos        (6UL)                     /*!< CAN1CLKSEL (Bit 6)                                    */
#define CLOCK_PFCSR_CAN1CLKSEL_Msk        (0xc0UL)                  /*!< CAN1CLKSEL (Bitfield-Mask: 0x03)                      */
#define CLOCK_PFCSR_CAN2CLKSEL_Pos        (8UL)                     /*!< CAN2CLKSEL (Bit 8)                                    */
#define CLOCK_PFCSR_CAN2CLKSEL_Msk        (0x300UL)                 /*!< CAN2CLKSEL (Bitfield-Mask: 0x03)                      */
#define CLOCK_PFCSR_TIMER0CLKSEL_Pos      (10UL)                    /*!< TIMER0CLKSEL (Bit 10)                                 */
#define CLOCK_PFCSR_TIMER0CLKSEL_Msk      (0xc00UL)                 /*!< TIMER0CLKSEL (Bitfield-Mask: 0x03)                    */
#define CLOCK_PFCSR_TIMER1CLKSEL_Pos      (12UL)                    /*!< TIMER1CLKSEL (Bit 12)                                 */
#define CLOCK_PFCSR_TIMER1CLKSEL_Msk      (0x3000UL)                /*!< TIMER1CLKSEL (Bitfield-Mask: 0x03)                    */
#define CLOCK_PFCSR_TIMER2CLKSEL_Pos      (14UL)                    /*!< TIMER2CLKSEL (Bit 14)                                 */
#define CLOCK_PFCSR_TIMER2CLKSEL_Msk      (0xc000UL)                /*!< TIMER2CLKSEL (Bitfield-Mask: 0x03)                    */
#define CLOCK_PFCSR_TIMER3CLKSEL_Pos      (16UL)                    /*!< TIMER3CLKSEL (Bit 16)                                 */
#define CLOCK_PFCSR_TIMER3CLKSEL_Msk      (0x30000UL)               /*!< TIMER3CLKSEL (Bitfield-Mask: 0x03)                    */
#define CLOCK_PFCSR_CMP0CLKSEL_Pos        (18UL)                    /*!< CMP0CLKSEL (Bit 18)                                   */
#define CLOCK_PFCSR_CMP0CLKSEL_Msk        (0xc0000UL)               /*!< CMP0CLKSEL (Bitfield-Mask: 0x03)                      */

/* =========================================================================================================================== */
/* ================                                            HAU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  DR  =========================================================== */
#define HAU_DR_DIVIDEND_Pos               (0UL)                     /*!< DIVIDEND (Bit 0)                                      */
#define HAU_DR_DIVIDEND_Msk               (0xffffffffUL)            /*!< DIVIDEND (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  DCR  ========================================================== */
#define HAU_DCR_DIVISOR_Pos               (0UL)                     /*!< DIVISOR (Bit 0)                                       */
#define HAU_DCR_DIVISOR_Msk               (0xffffffUL)              /*!< DIVISOR (Bitfield-Mask: 0xffffff)                     */
#define HAU_DCR_SIGN_SEL_Pos              (24UL)                    /*!< SIGN_SEL (Bit 24)                                     */
#define HAU_DCR_SIGN_SEL_Msk              (0x1000000UL)             /*!< SIGN_SEL (Bitfield-Mask: 0x01)                        */
#define HAU_DCR_RESULT_SEL_Pos            (25UL)                    /*!< RESULT_SEL (Bit 25)                                   */
#define HAU_DCR_RESULT_SEL_Msk            (0x2000000UL)             /*!< RESULT_SEL (Bitfield-Mask: 0x01)                      */
#define HAU_DCR_DENDS_Pos                 (26UL)                    /*!< DENDS (Bit 26)                                        */
#define HAU_DCR_DENDS_Msk                 (0x7c000000UL)            /*!< DENDS (Bitfield-Mask: 0x1f)                           */
/* ==========================================================  DRR  ========================================================== */
#define HAU_DRR_DIVRESULT_Pos             (0UL)                     /*!< DIVRESULT (Bit 0)                                     */
#define HAU_DRR_DIVRESULT_Msk             (0xffffffffUL)            /*!< DIVRESULT (Bitfield-Mask: 0xffffffff)                 */
/* ==========================================================  SR  =========================================================== */
#define HAU_SR_SQRT_Pos                   (0UL)                     /*!< SQRT (Bit 0)                                          */
#define HAU_SR_SQRT_Msk                   (0xffffffffUL)            /*!< SQRT (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  SRR  ========================================================== */
#define HAU_SRR_SQRT_RESULT_Pos           (0UL)                     /*!< SQRT_RESULT (Bit 0)                                   */
#define HAU_SRR_SQRT_RESULT_Msk           (0xffffUL)                /*!< SQRT_RESULT (Bitfield-Mask: 0xffff)                   */
/* ==========================================================  SSR  ========================================================== */
#define HAU_SSR_SQROOTX_Pos               (0UL)                     /*!< SQROOTX (Bit 0)                                       */
#define HAU_SSR_SQROOTX_Msk               (0xffffUL)                /*!< SQROOTX (Bitfield-Mask: 0xffff)                       */
#define HAU_SSR_SQROOTY_Pos               (16UL)                    /*!< SQROOTY (Bit 16)                                      */
#define HAU_SSR_SQROOTY_Msk               (0xffff0000UL)            /*!< SQROOTY (Bitfield-Mask: 0xffff)                       */
/* =========================================================  SSRR  ========================================================== */
#define HAU_SSRR_SQROOT_RESULT_Pos        (0UL)                     /*!< SQROOT_RESULT (Bit 0)                                 */
#define HAU_SSRR_SQROOT_RESULT_Msk        (0xffffUL)                /*!< SQROOT_RESULT (Bitfield-Mask: 0xffff)                 */
/* ==========================================================  SCR  ========================================================== */
#define HAU_SCR_SINCOS_Pos                (0UL)                     /*!< SINCOS (Bit 0)                                        */
#define HAU_SCR_SINCOS_Msk                (0xffffUL)                /*!< SINCOS (Bitfield-Mask: 0xffff)                        */
/* =========================================================  SCRR  ========================================================== */
#define HAU_SCRR_SIN_RESULT_Pos           (0UL)                     /*!< SIN_RESULT (Bit 0)                                    */
#define HAU_SCRR_SIN_RESULT_Msk           (0xffffUL)                /*!< SIN_RESULT (Bitfield-Mask: 0xffff)                    */
#define HAU_SCRR_COS_RESULT_Pos           (16UL)                    /*!< COS_RESULT (Bit 16)                                   */
#define HAU_SCRR_COS_RESULT_Msk           (0xffff0000UL)            /*!< COS_RESULT (Bitfield-Mask: 0xffff)                    */
/* ==========================================================  AR  =========================================================== */
#define HAU_AR_ARCTANX_Pos                (0UL)                     /*!< ARCTANX (Bit 0)                                       */
#define HAU_AR_ARCTANX_Msk                (0xffffUL)                /*!< ARCTANX (Bitfield-Mask: 0xffff)                       */
#define HAU_AR_ARCTANY_Pos                (16UL)                    /*!< ARCTANY (Bit 16)                                      */
#define HAU_AR_ARCTANY_Msk                (0xffff0000UL)            /*!< ARCTANY (Bitfield-Mask: 0xffff)                       */
/* ==========================================================  ARR  ========================================================== */
#define HAU_ARR_ARCTAN_RESULT_Pos         (0UL)                     /*!< ARCTAN_RESULT (Bit 0)                                 */
#define HAU_ARR_ARCTAN_RESULT_Msk         (0xffffUL)                /*!< ARCTAN_RESULT (Bitfield-Mask: 0xffff)                 */
/* ========================================================  STATUS  ========================================================= */
#define HAU_STATUS_DIVERR_Pos             (0UL)                     /*!< DIVERR (Bit 0)                                        */
#define HAU_STATUS_DIVERR_Msk             (0x1UL)                   /*!< DIVERR (Bitfield-Mask: 0x01)                          */
#define HAU_STATUS_DIVBUSY_Pos            (1UL)                     /*!< DIVBUSY (Bit 1)                                       */
#define HAU_STATUS_DIVBUSY_Msk            (0x2UL)                   /*!< DIVBUSY (Bitfield-Mask: 0x01)                         */
#define HAU_STATUS_SQRTBUSY_Pos           (2UL)                     /*!< SQRTBUSY (Bit 2)                                      */
#define HAU_STATUS_SQRTBUSY_Msk           (0x4UL)                   /*!< SQRTBUSY (Bitfield-Mask: 0x01)                        */
#define HAU_STATUS_SQROOTBUSY_Pos         (3UL)                     /*!< SQROOTBUSY (Bit 3)                                    */
#define HAU_STATUS_SQROOTBUSY_Msk         (0x8UL)                   /*!< SQROOTBUSY (Bitfield-Mask: 0x01)                      */
#define HAU_STATUS_SINCOSBUSY_Pos         (4UL)                     /*!< SINCOSBUSY (Bit 4)                                    */
#define HAU_STATUS_SINCOSBUSY_Msk         (0x10UL)                  /*!< SINCOSBUSY (Bitfield-Mask: 0x01)                      */
#define HAU_STATUS_ARCTANBUSY_Pos         (5UL)                     /*!< ARCTANBUSY (Bit 5)                                    */
#define HAU_STATUS_ARCTANBUSY_Msk         (0x20UL)                  /*!< ARCTANBUSY (Bitfield-Mask: 0x01)                      */

/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

#define DMA_GLB_ENABLE_ENABLE_Pos         (0UL)                     /*!< ENABLE (Bit 0)                                        */
#define DMA_GLB_ENABLE_ENABLE_Msk         (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* =======================================================  CH_ENABLE  ======================================================= */
#define DMA_CH_ENABLE_CH_ENABLE_Pos       (0UL)                     /*!< CH_ENABLE (Bit 0)                                     */
#define DMA_CH_ENABLE_CH_ENABLE_Msk       (0xfUL)                   /*!< CH_ENABLE (Bitfield-Mask: 0x0f)                       */
/* =========================================================  SWREQ  ========================================================= */
#define DMA_SWREQ_SWREQ_Pos               (0UL)                     /*!< SWREQ (Bit 0)                                         */
#define DMA_SWREQ_SWREQ_Msk               (0x3fffffUL)              /*!< SWREQ (Bitfield-Mask: 0x3fffff)                       */

/* =========================================================================================================================== */
/* ================                                           DMA_CH                                        ================ */
/* =========================================================================================================================== */
/* ==========================================================  LLI  ========================================================== */
#define DMA_CH_LLI_LLI_Pos               (2UL)                     /*!< LLI (Bit 2)                                           */
#define DMA_CH_LLI_LLI_Msk               (0xfffffffcUL)            /*!< LLI (Bitfield-Mask: 0x3fffffff)                       */
/* =========================================================  CTRL  ========================================================== */
#define DMA_CHCR_TRANSFERSIZE_Pos        (0UL)                     /*!< TRANSFERSIZE (Bit 0)                                  */
#define DMA_CHCR_TRANSFERSIZE_Msk        (0xfffUL)                 /*!< TRANSFERSIZE (Bitfield-Mask: 0xfff)                   */
#define DMA_CHCR_SWIDTH_Pos              (18UL)                    /*!< SWIDTH (Bit 18)                                       */
#define DMA_CHCR_SWIDTH_Msk              (0x1c0000UL)              /*!< SWIDTH (Bitfield-Mask: 0x07)                          */
#define DMA_CHCR_DWIDTH_Pos              (21UL)                    /*!< DWIDTH (Bit 21)                                       */
#define DMA_CHCR_DWIDTH_Msk              (0xe00000UL)              /*!< DWIDTH (Bitfield-Mask: 0x07)                          */
#define DMA_CHCR_SI_Pos                  (26UL)                    /*!< SI (Bit 26)                                           */
#define DMA_CHCR_SI_Msk                  (0x4000000UL)             /*!< SI (Bitfield-Mask: 0x01)                              */
#define DMA_CHCR_DI_Pos                  (27UL)                    /*!< DI (Bit 27)                                           */
#define DMA_CHCR_DI_Msk                  (0x8000000UL)             /*!< DI (Bitfield-Mask: 0x01)                              */
#define DMA_CHCR_LLIITC_Pos              (31UL)                    /*!< LLIITC (Bit 31)                                       */
#define DMA_CHCR_LLIITC_Msk              (0x80000000UL)            /*!< LLIITC (Bitfield-Mask: 0x01)                          */
/* =========================================================  CONF  ========================================================== */
#define DMA_CHCONF_ENABLE_Pos            (0UL)                     /*!< ENABLE (Bit 0)                                        */
#define DMA_CHCONF_ENABLE_Msk            (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
#define DMA_CHCONF_SRCPERIPH_Pos         (1UL)                     /*!< SRCPERIPH (Bit 1)                                     */
#define DMA_CHCONF_SRCPERIPH_Msk         (0x3eUL)                  /*!< SRCPERIPH (Bitfield-Mask: 0x1f)                       */
#define DMA_CHCONF_DESTPERIPH_Pos        (6UL)                     /*!< DESTPERIPH (Bit 6)                                    */
#define DMA_CHCONF_DESTPERIPH_Msk        (0x7c0UL)                 /*!< DESTPERIPH (Bitfield-Mask: 0x1f)                      */
#define DMA_CHCONF_FLOWCTRL_Pos          (11UL)                    /*!< FLOWCTRL (Bit 11)                                     */
#define DMA_CHCONF_FLOWCTRL_Msk          (0x3800UL)                /*!< FLOWCTRL (Bitfield-Mask: 0x07)                        */
#define DMA_CHCONF_TEIE_Pos              (14UL)                    /*!< TEIE (Bit 14)                                         */
#define DMA_CHCONF_TEIE_Msk              (0x4000UL)                /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CHCONF_TCIE_Pos              (15UL)                    /*!< TCIE (Bit 15)                                         */
#define DMA_CHCONF_TCIE_Msk              (0x8000UL)                /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CHCONF_ACTIVE_Pos            (17UL)                    /*!< ACTIVE (Bit 17)                                       */
#define DMA_CHCONF_ACTIVE_Msk            (0x20000UL)               /*!< ACTIVE (Bitfield-Mask: 0x01)                          */
#define DMA_CHCONF_HALT_Pos              (18UL)                    /*!< HALT (Bit 18)                                         */
#define DMA_CHCONF_HALT_Msk              (0x40000UL)               /*!< HALT (Bitfield-Mask: 0x01)                            */
/* ==========================================================  STS  ========================================================== */
#define DMA_CHSR_DONE_Pos                (0UL)                     /*!< DONE (Bit 0)                                          */
#define DMA_CHSR_DONE_Msk                (0x1UL)                   /*!< DONE (Bitfield-Mask: 0x01)                            */
#define DMA_CHSR_ERR_Pos                 (1UL)                     /*!< ERR (Bit 1)                                           */
#define DMA_CHSR_ERR_Msk                 (0x2UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           UART                                           ================ */
/* =========================================================================================================================== */

/* =======================================================  UART_CTRL  ======================================================== */
#define UART_UCR_DWIDTH_Pos              (0UL)                     /*!< DWIDTH (Bit 0)                                        */
#define UART_UCR_DWIDTH_Msk              (0x3UL)                   /*!< DWIDTH (Bitfield-Mask: 0x03)                          */
#define UART_UCR_REMSBF_Pos              (2UL)                     /*!< REMSBF (Bit 2)                                        */
#define UART_UCR_REMSBF_Msk              (0x4UL)                   /*!< REMSBF (Bitfield-Mask: 0x01)                          */
#define UART_UCR_TEMSBF_Pos              (3UL)                     /*!< TEMSBF (Bit 3)                                        */
#define UART_UCR_TEMSBF_Msk              (0x8UL)                   /*!< TEMSBF (Bitfield-Mask: 0x01)                          */
#define UART_UCR_STP_Pos                 (4UL)                     /*!< STP (Bit 4)                                           */
#define UART_UCR_STP_Msk                 (0x10UL)                  /*!< STP (Bitfield-Mask: 0x01)                             */
#define UART_UCR_RIDLEN_Pos              (5UL)                     /*!< RIDLEN (Bit 5)                                        */
#define UART_UCR_RIDLEN_Msk              (0x20UL)                  /*!< RIDLEN (Bitfield-Mask: 0x01)                          */
#define UART_UCR_LOOPEN_Pos              (6UL)                     /*!< LOOPEN (Bit 6)                                        */
#define UART_UCR_LOOPEN_Msk              (0x40UL)                  /*!< LOOPEN (Bitfield-Mask: 0x01)                          */
#define UART_UCR_REN_Pos                 (8UL)                     /*!< REN (Bit 8)                                           */
#define UART_UCR_REN_Msk                 (0x100UL)                 /*!< REN (Bitfield-Mask: 0x01)                             */
#define UART_UCR_TEN_Pos                 (9UL)                     /*!< TEN (Bit 9)                                           */
#define UART_UCR_TEN_Msk                 (0x200UL)                 /*!< TEN (Bitfield-Mask: 0x01)                             */
#define UART_UCR_RDMAEN_Pos              (10UL)                    /*!< RDMAEN (Bit 10)                                       */
#define UART_UCR_RDMAEN_Msk              (0x400UL)                 /*!< RDMAEN (Bitfield-Mask: 0x01)                          */
#define UART_UCR_TDMAEN_Pos              (11UL)                    /*!< TDMAEN (Bit 11)                                       */
#define UART_UCR_TDMAEN_Msk              (0x800UL)                 /*!< TDMAEN (Bitfield-Mask: 0x01)                          */
#define UART_UCR_RINVT_Pos               (12UL)                    /*!< RINVT (Bit 12)                                        */
#define UART_UCR_RINVT_Msk               (0x1000UL)                /*!< RINVT (Bitfield-Mask: 0x01)                           */
#define UART_UCR_TINVT_Pos               (13UL)                    /*!< TINVT (Bit 13)                                        */
#define UART_UCR_TINVT_Msk               (0x2000UL)                /*!< TINVT (Bitfield-Mask: 0x01)                           */
#define UART_UCR_PEN_Pos                 (16UL)                    /*!< PEN (Bit 16)                                          */
#define UART_UCR_PEN_Msk                 (0x10000UL)               /*!< PEN (Bitfield-Mask: 0x01)                             */
#define UART_UCR_PTYPE_Pos               (17UL)                    /*!< PTYPE (Bit 17)                                        */
#define UART_UCR_PTYPE_Msk               (0x20000UL)               /*!< PTYPE (Bitfield-Mask: 0x01)                           */
/* ========================================================  LIN_CTRL ======================================================== */
#define UART_LCR_LBKLTX_Pos              (0UL)                     /*!< LBKLTX (Bit 0)                                        */
#define UART_LCR_LBKLTX_Msk              (0xfUL)                   /*!< LBKLTX (Bitfield-Mask: 0x0f)                          */
#define UART_LCR_LBKLCK_Pos              (4UL)                     /*!< LBKLCK (Bit 4)                                        */
#define UART_LCR_LBKLCK_Msk              (0x10UL)                  /*!< LBKLCK (Bitfield-Mask: 0x01)                          */
#define UART_LCR_LEN_Pos                 (5UL)                     /*!< LEN (Bit 5)                                           */
#define UART_LCR_LEN_Msk                 (0x20UL)                  /*!< LEN (Bitfield-Mask: 0x01)                             */
#define UART_LCR_LABREN_Pos              (6UL)                     /*!< LABREN (Bit 6)                                        */
#define UART_LCR_LABREN_Msk              (0x40UL)                  /*!< LABREN (Bitfield-Mask: 0x01)                          */
#define UART_LCR_LSYCEIEN_Pos            (7UL)                     /*!< LSYCEIEN (Bit 7)                                      */
#define UART_LCR_LSYCEIEN_Msk            (0x80UL)                  /*!< LSYCEIEN (Bitfield-Mask: 0x01)                        */
#define UART_LCR_LBKIEN_Pos              (8UL)                     /*!< LBKIEN (Bit 8)                                        */
#define UART_LCR_LBKIEN_Msk              (0x100UL)                 /*!< LBKIEN (Bitfield-Mask: 0x01)                          */
#define UART_LCR_LBUSEIEN_Pos            (9UL)                     /*!< LBUSEIEN (Bit 9)                                      */
#define UART_LCR_LBUSEIEN_Msk            (0x200UL)                 /*!< LBUSEIEN (Bitfield-Mask: 0x01)                        */
#define UART_LCR_LTBK_Pos                (16UL)                    /*!< LTBK (Bit 16)                                         */
#define UART_LCR_LTBK_Msk                (0x10000UL)               /*!< LTBK (Bitfield-Mask: 0x01)                            */
/* =======================================================  BAUD  ============================================================ */
#define UART_BAUD_BRINT_Pos              (0UL)                     /*!< BRINT (Bit 0)                                         */
#define UART_BAUD_BRINT_Msk              (0xffffUL)                /*!< BRINT (Bitfield-Mask: 0xffff)                         */
#define UART_BAUD_BRDEC_Pos              (16UL)                    /*!< BRDEC (Bit 16)                                        */
#define UART_BAUD_BRDEC_Msk              (0x1f0000UL)              /*!< BRDEC (Bitfield-Mask: 0x1f)                           */
#define UART_BAUD_BROSR_Pos              (21UL)                    /*!< BROSR (Bit 21)                                        */
#define UART_BAUD_BROSR_Msk              (0x200000UL)              /*!< BROSR (Bitfield-Mask: 0x01)                           */
/* ========================================================= SR  ========================================================= */
#define UART_SR_TCF_Pos                  (0UL)                     /*!< TCF (Bit 0)                                           */
#define UART_SR_TCF_Msk                  (0x1UL)                   /*!< TCF (Bitfield-Mask: 0x01)                             */
#define UART_SR_TFF_Pos                  (1UL)                     /*!< TFF (Bit 1)                                           */
#define UART_SR_TFF_Msk                  (0x2UL)                   /*!< TFF (Bitfield-Mask: 0x01)                             */
#define UART_SR_TEF_Pos                  (2UL)                     /*!< TEF (Bit 2)                                           */
#define UART_SR_TEF_Msk                  (0x4UL)                   /*!< TEF (Bitfield-Mask: 0x01)                             */
#define UART_SR_NOISEF_Pos               (3UL)                     /*!< NOISEF (Bit 3)                                        */
#define UART_SR_NOISEF_Msk               (0x8UL)                   /*!< NOISEF (Bitfield-Mask: 0x01)                          */
#define UART_SR_RPEF_Pos                 (4UL)                     /*!< RPEF (Bit 4)                                          */
#define UART_SR_RPEF_Msk                 (0x10UL)                  /*!< RPEF (Bitfield-Mask: 0x01)                            */
#define UART_SR_RFEF_Pos                 (5UL)                     /*!< RFEF (Bit 5)                                          */
#define UART_SR_RFEF_Msk                 (0x20UL)                  /*!< RFEF (Bitfield-Mask: 0x01)                            */
#define UART_SR_RNEF_Pos                 (6UL)                     /*!< RNEF (Bit 6)                                          */
#define UART_SR_RNEF_Msk                 (0x40UL)                  /*!< RNEF (Bitfield-Mask: 0x01)                            */
#define UART_SR_ROFEF_Pos                (7UL)                     /*!< ROFEF (Bit 7)                                         */
#define UART_SR_ROFEF_Msk                (0x80UL)                  /*!< ROFEF (Bitfield-Mask: 0x01)                           */
#define UART_SR_RIDLEF_Pos               (8UL)                     /*!< RIDLEF (Bit 8)                                        */
#define UART_SR_RIDLEF_Msk               (0x100UL)                 /*!< RIDLEF (Bitfield-Mask: 0x01)                          */
#define UART_SR_RLOWEF_Pos               (9UL)                     /*!< RLOWEF (Bit 9)                                        */
#define UART_SR_RLOWEF_Msk               (0x200UL)                 /*!< RLOWEF (Bitfield-Mask: 0x01)                          */
#define UART_SR_BUSYF_Pos                (10UL)                    /*!< BUSYF (Bit 10)                                        */
#define UART_SR_BUSYF_Msk                (0x400UL)                 /*!< BUSYF (Bitfield-Mask: 0x01)                           */
#define UART_SR_LSYCEF_Pos               (16UL)                    /*!< LSYCEF (Bit 16)                                       */
#define UART_SR_LSYCEF_Msk               (0x10000UL)               /*!< LSYCEF (Bitfield-Mask: 0x01)                          */
#define UART_SR_LBKF_Pos                 (17UL)                    /*!< LBKF (Bit 17)                                         */
#define UART_SR_LBKF_Msk                 (0x20000UL)               /*!< LBKF (Bitfield-Mask: 0x01)                            */
#define UART_SR_LBUSEF_Pos               (18UL)                    /*!< LBUSEF (Bit 18)                                       */
#define UART_SR_LBUSEF_Msk               (0x40000UL)               /*!< LBUSEF (Bitfield-Mask: 0x01)                          */
/* ========================================================  IER   ========================================================== */
#define UART_IER_TCIEN_Pos               (0UL)                     /*!< TCIEN (Bit 0)                                         */
#define UART_IER_TCIEN_Msk               (0x1UL)                   /*!< TCIEN (Bitfield-Mask: 0x01)                           */
#define UART_IER_TFIEN_Pos               (1UL)                     /*!< TFIEN (Bit 1)                                         */
#define UART_IER_TFIEN_Msk               (0x2UL)                   /*!< TFIEN (Bitfield-Mask: 0x01)                           */
#define UART_IER_TEIEN_Pos               (2UL)                     /*!< TEIEN (Bit 2)                                         */
#define UART_IER_TEIEN_Msk               (0x4UL)                   /*!< TEIEN (Bitfield-Mask: 0x01)                           */
#define UART_IER_NOISEIEN_Pos            (3UL)                     /*!< NOISEIEN (Bit 3)                                      */
#define UART_IER_NOISEIEN_Msk            (0x8UL)                   /*!< NOISEIEN (Bitfield-Mask: 0x01)                        */
#define UART_IER_RPEIEN_Pos              (4UL)                     /*!< RPEIEN (Bit 4)                                        */
#define UART_IER_RPEIEN_Msk              (0x10UL)                  /*!< RPEIEN (Bitfield-Mask: 0x01)                          */
#define UART_IER_RFEIEN_Pos              (5UL)                     /*!< RFEIEN (Bit 5)                                        */
#define UART_IER_RFEIEN_Msk              (0x20UL)                  /*!< RFEIEN (Bitfield-Mask: 0x01)                          */
#define UART_IER_RNEIEN_Pos              (6UL)                     /*!< RNEIEN (Bit 6)                                        */
#define UART_IER_RNEIEN_Msk              (0x40UL)                  /*!< RNEIEN (Bitfield-Mask: 0x01)                          */
#define UART_IER_ROFEIEN_Pos             (7UL)                     /*!< ROFEIEN (Bit 7)                                       */
#define UART_IER_ROFEIEN_Msk             (0x80UL)                  /*!< ROFEIEN (Bitfield-Mask: 0x01)                         */
#define UART_IER_RIDLIEN_Pos             (8UL)                     /*!< RIDLIEN (Bit 8)                                       */
#define UART_IER_RIDLIEN_Msk             (0x100UL)                 /*!< RIDLIEN (Bitfield-Mask: 0x01)                         */
/* =========================================================  DATA  ==========================================================*/
#define UART_DATA_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define UART_DATA_DATA_Msk               (0x1ffUL)                 /*!< DATA (Bitfield-Mask: 0x1ff)                           */


/* =========================================================================================================================== */
/* ================                                            ERM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SCR  ========================================================== */
#define ERM_SCR_SSCIE_Pos                 (0UL)                     /*!< SSCIE (Bit 0)                                         */
#define ERM_SCR_SSCIE_Msk                 (0x1UL)                   /*!< SSCIE (Bitfield-Mask: 0x01)                           */
#define ERM_SCR_SNCIE_Pos                 (1UL)                     /*!< SNCIE (Bit 1)                                         */
#define ERM_SCR_SNCIE_Msk                 (0x2UL)                   /*!< SNCIE (Bitfield-Mask: 0x01)                           */
#define ERM_SCR_SEENE_Pos                 (2UL)                     /*!< SEENE (Bit 2)                                         */
#define ERM_SCR_SEENE_Msk                 (0x4UL)                   /*!< SEENE (Bitfield-Mask: 0x01)                           */
#define ERM_SCR_SEDEE_Pos                 (3UL)                     /*!< SEDEE (Bit 3)                                         */
#define ERM_SCR_SEDEE_Msk                 (0x8UL)                   /*!< SEDEE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SSR  ========================================================== */
#define ERM_SSR_SSBC_Pos                  (0UL)                     /*!< SSBC (Bit 0)                                          */
#define ERM_SSR_SSBC_Msk                  (0x1UL)                   /*!< SSBC (Bitfield-Mask: 0x01)                            */
#define ERM_SSR_SNCE_Pos                  (1UL)                     /*!< SNCE (Bit 1)                                          */
#define ERM_SSR_SNCE_Msk                  (0x2UL)                   /*!< SNCE (Bitfield-Mask: 0x01)                            */
/* =========================================================  SSEA  ========================================================== */
#define ERM_SSEA_EADR_Pos                 (0UL)                     /*!< EADR (Bit 0)                                          */
#define ERM_SSEA_EADR_Msk                 (0xffffffffUL)            /*!< EADR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  SNEA  ========================================================== */
#define ERM_SNEA_EADR_Pos                 (0UL)                     /*!< EADR (Bit 0)                                          */
#define ERM_SNEA_EADR_Msk                 (0xffffffffUL)            /*!< EADR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  PFCR  ========================================================== */
#define ERM_PFCR_PFSCIE_Pos               (0UL)                     /*!< PFSCIE (Bit 0)                                        */
#define ERM_PFCR_PFSCIE_Msk               (0x1UL)                   /*!< PFSCIE (Bitfield-Mask: 0x01)                          */
#define ERM_PFCR_PFNCIE_Pos               (1UL)                     /*!< PFNCIE (Bit 1)                                        */
#define ERM_PFCR_PFNCIE_Msk               (0x2UL)                   /*!< PFNCIE (Bitfield-Mask: 0x01)                          */
#define ERM_PFCR_PFEENE_Pos               (2UL)                     /*!< PFEENE (Bit 2)                                        */
#define ERM_PFCR_PFEENE_Msk               (0x4UL)                   /*!< PFEENE (Bitfield-Mask: 0x01)                          */
#define ERM_PFCR_PFEDEE_Pos               (3UL)                     /*!< PFEDEE (Bit 3)                                        */
#define ERM_PFCR_PFEDEE_Msk               (0x8UL)                   /*!< PFEDEE (Bitfield-Mask: 0x01)                          */
/* =========================================================  PFSR  ========================================================== */
#define ERM_PFSR_PFSBC_Pos                (0UL)                     /*!< PFSBC (Bit 0)                                         */
#define ERM_PFSR_PFSBC_Msk                (0x1UL)                   /*!< PFSBC (Bitfield-Mask: 0x01)                           */
#define ERM_PFSR_PFNCE_Pos                (1UL)                     /*!< PFNCE (Bit 1)                                         */
#define ERM_PFSR_PFNCE_Msk                (0x2UL)                   /*!< PFNCE (Bitfield-Mask: 0x01)                           */
/* =========================================================  PFSEA  ========================================================= */
#define ERM_PFSEA_PEADR_Pos               (0UL)                     /*!< PEADR (Bit 0)                                         */
#define ERM_PFSEA_PEADR_Msk               (0xffffffffUL)            /*!< PEADR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  PFNEA  ========================================================= */
#define ERM_PFNEA_EADR_Pos                (0UL)                     /*!< EADR (Bit 0)                                          */
#define ERM_PFNEA_EADR_Msk                (0xffffffffUL)            /*!< EADR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DFCR  ========================================================== */
#define ERM_DFCR_DFSCIE_Pos               (0UL)                     /*!< DFSCIE (Bit 0)                                        */
#define ERM_DFCR_DFSCIE_Msk               (0x1UL)                   /*!< DFSCIE (Bitfield-Mask: 0x01)                          */
#define ERM_DFCR_DFNCIE_Pos               (1UL)                     /*!< DFNCIE (Bit 1)                                        */
#define ERM_DFCR_DFNCIE_Msk               (0x2UL)                   /*!< DFNCIE (Bitfield-Mask: 0x01)                          */
#define ERM_DFCR_DFEENE_Pos               (2UL)                     /*!< DFEENE (Bit 2)                                        */
#define ERM_DFCR_DFEENE_Msk               (0x4UL)                   /*!< DFEENE (Bitfield-Mask: 0x01)                          */
#define ERM_DFCR_DFEDEE_Pos               (3UL)                     /*!< DFEDEE (Bit 3)                                        */
#define ERM_DFCR_DFEDEE_Msk               (0x8UL)                   /*!< DFEDEE (Bitfield-Mask: 0x01)                          */
/* =========================================================  DFSR  ========================================================== */
#define ERM_DFSR_DFSBC_Pos                (0UL)                     /*!< DFSBC (Bit 0)                                         */
#define ERM_DFSR_DFSBC_Msk                (0x1UL)                   /*!< DFSBC (Bitfield-Mask: 0x01)                           */
#define ERM_DFSR_DFNCE_Pos                (1UL)                     /*!< DFNCE (Bit 1)                                         */
#define ERM_DFSR_DFNCE_Msk                (0x2UL)                   /*!< DFNCE (Bitfield-Mask: 0x01)                           */
/* =========================================================  DFSEA  ========================================================= */
#define ERM_DFSEA_DEADR_Pos               (0UL)                     /*!< DEADR (Bit 0)                                         */
#define ERM_DFSEA_DEADR_Msk               (0xffffffffUL)            /*!< DEADR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DFNEA  ========================================================= */
#define ERM_DFNEA_DEADR_Pos               (0UL)                     /*!< DEADR (Bit 0)                                         */
#define ERM_DFNEA_DEADR_Msk               (0xffffffffUL)            /*!< DEADR (Bitfield-Mask: 0xffffffff)                     */

/* =========================================================================================================================== */
/* ================                                           IPWM                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  GPSC  ========================================================== */
#define IPWM_GPSC_GPSC_Pos                (0UL)                     /*!< GPSC (Bit 0)                                          */
#define IPWM_GPSC_GPSC_Msk                (0xffUL)                  /*!< GPSC (Bitfield-Mask: 0xff)                            */
#define IPWM_GPSC_GPSCEN_Pos              (16UL)                    /*!< GPSCEN (Bit 16)                                       */
#define IPWM_GPSC_GPSCEN_Msk              (0x10000UL)               /*!< GPSCEN (Bitfield-Mask: 0x01)                          */
/* =======================================================   CNT0SC  ========================================================= */
#define IPWM_CNT0SC_CNTEN_Pos             (0UL)                     /*!< CNTEN (Bit 0)                                         */
#define IPWM_CNT0SC_CNTEN_Msk             (0x1UL)                   /*!< CNTEN (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT0SC_CPWMS_Pos             (1UL)                     /*!< CPWMS (Bit 1)                                         */
#define IPWM_CNT0SC_CPWMS_Msk             (0x2UL)                   /*!< CPWMS (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT0SC_COIE_Pos              (4UL)                     /*!< COIE (Bit 4)                                          */
#define IPWM_CNT0SC_COIE_Msk              (0x10UL)                  /*!< COIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT0SC_CUIE_Pos              (5UL)                     /*!< CUIE (Bit 5)                                          */
#define IPWM_CNT0SC_CUIE_Msk              (0x20UL)                  /*!< CUIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT0SC_COFNUM_Pos            (8UL)                     /*!< COFNUM (Bit 8)                                        */
#define IPWM_CNT0SC_COFNUM_Msk            (0x1f00UL)                /*!< COFNUM (Bitfield-Mask: 0x3f)                          */
#define IPWM_CNT0SC_COF_Pos               (14UL)                    /*!< COF (Bit 14)                                          */
#define IPWM_CNT0SC_COF_Msk               (0x4000UL)                /*!< COF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT0SC_CUF_Pos               (15UL)                    /*!< CUF (Bit 15)                                          */
#define IPWM_CNT0SC_CUF_Msk               (0x8000UL)                /*!< CUF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT0SC_LPSC_Pos              (16UL)                    /*!< LPSC (Bit 16)                                         */
#define IPWM_CNT0SC_LPSC_Msk              (0xf0000UL)               /*!< LPSC (Bitfield-Mask: 0x0f)                            */
/* ========================================================  CNT1SC  ========================================================= */
#define IPWM_CNT1SC_CNTEN_Pos             (0UL)                     /*!< CNTEN (Bit 0)                                         */
#define IPWM_CNT1SC_CNTEN_Msk             (0x1UL)                   /*!< CNTEN (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT1SC_CPWMS_Pos             (1UL)                     /*!< CPWMS (Bit 1)                                         */
#define IPWM_CNT1SC_CPWMS_Msk             (0x2UL)                   /*!< CPWMS (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT1SC_COIE_Pos              (4UL)                     /*!< COIE (Bit 4)                                          */
#define IPWM_CNT1SC_COIE_Msk              (0x10UL)                  /*!< COIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT1SC_CUIE_Pos              (5UL)                     /*!< CUIE (Bit 5)                                          */
#define IPWM_CNT1SC_CUIE_Msk              (0x20UL)                  /*!< CUIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT1SC_COFNUM_Pos            (8UL)                     /*!< COFNUM (Bit 8)                                        */
#define IPWM_CNT1SC_COFNUM_Msk            (0x1f00UL)                /*!< COFNUM (Bitfield-Mask: 0x3f)                          */
#define IPWM_CNT1SC_COF_Pos               (14UL)                    /*!< COF (Bit 14)                                          */
#define IPWM_CNT1SC_COF_Msk               (0x4000UL)                /*!< COF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT1SC_CUF_Pos               (15UL)                    /*!< CUF (Bit 15)                                          */
#define IPWM_CNT1SC_CUF_Msk               (0x8000UL)                /*!< CUF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT1SC_LPSC_Pos              (16UL)                    /*!< LPSC (Bit 16)                                         */
#define IPWM_CNT1SC_LPSC_Msk              (0xf0000UL)               /*!< LPSC (Bitfield-Mask: 0x0f)                            */
/* ========================================================  CNT2SC  ========================================================= */
#define IPWM_CNT2SC_CNTEN_Pos             (0UL)                     /*!< CNTEN (Bit 0)                                         */
#define IPWM_CNT2SC_CNTEN_Msk             (0x1UL)                   /*!< CNTEN (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT2SC_CPWMS_Pos             (1UL)                     /*!< CPWMS (Bit 1)                                         */
#define IPWM_CNT2SC_CPWMS_Msk             (0x2UL)                   /*!< CPWMS (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT2SC_COIE_Pos              (4UL)                     /*!< COIE (Bit 4)                                          */
#define IPWM_CNT2SC_COIE_Msk              (0x10UL)                  /*!< COIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT2SC_CUIE_Pos              (5UL)                     /*!< CUIE (Bit 5)                                          */
#define IPWM_CNT2SC_CUIE_Msk              (0x20UL)                  /*!< CUIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT2SC_COFNUM_Pos            (8UL)                     /*!< COFNUM (Bit 8)                                        */
#define IPWM_CNT2SC_COFNUM_Msk            (0x1f00UL)                /*!< COFNUM (Bitfield-Mask: 0x3f)                          */
#define IPWM_CNT2SC_COF_Pos               (14UL)                    /*!< COF (Bit 14)                                          */
#define IPWM_CNT2SC_COF_Msk               (0x4000UL)                /*!< COF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT2SC_CUF_Pos               (15UL)                    /*!< CUF (Bit 15)                                          */
#define IPWM_CNT2SC_CUF_Msk               (0x8000UL)                /*!< CUF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT2SC_LPSC_Pos              (16UL)                    /*!< LPSC (Bit 16)                                         */
#define IPWM_CNT2SC_LPSC_Msk              (0xf0000UL)               /*!< LPSC (Bitfield-Mask: 0x0f)                            */
/* ========================================================  CNT3SC  ========================================================= */
#define IPWM_CNT3SC_CNTEN_Pos             (0UL)                     /*!< CNTEN (Bit 0)                                         */
#define IPWM_CNT3SC_CNTEN_Msk             (0x1UL)                   /*!< CNTEN (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT3SC_CPWMS_Pos             (1UL)                     /*!< CPWMS (Bit 1)                                         */
#define IPWM_CNT3SC_CPWMS_Msk             (0x2UL)                   /*!< CPWMS (Bitfield-Mask: 0x01)                           */
#define IPWM_CNT3SC_COIE_Pos              (4UL)                     /*!< COIE (Bit 4)                                          */
#define IPWM_CNT3SC_COIE_Msk              (0x10UL)                  /*!< COIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT3SC_CUIE_Pos              (5UL)                     /*!< CUIE (Bit 5)                                          */
#define IPWM_CNT3SC_CUIE_Msk              (0x20UL)                  /*!< CUIE (Bitfield-Mask: 0x01)                            */
#define IPWM_CNT3SC_COFNUM_Pos            (8UL)                     /*!< COFNUM (Bit 8)                                        */
#define IPWM_CNT3SC_COFNUM_Msk            (0x1f00UL)                /*!< COFNUM (Bitfield-Mask: 0x3f)                          */
#define IPWM_CNT3SC_COF_Pos               (14UL)                    /*!< COF (Bit 14)                                          */
#define IPWM_CNT3SC_COF_Msk               (0x4000UL)                /*!< COF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT3SC_CUF_Pos               (15UL)                    /*!< CUF (Bit 15)                                          */
#define IPWM_CNT3SC_CUF_Msk               (0x8000UL)                /*!< CUF (Bitfield-Mask: 0x01)                             */
#define IPWM_CNT3SC_LPSC_Pos              (16UL)                    /*!< LPSC (Bit 16)                                         */
#define IPWM_CNT3SC_LPSC_Msk              (0xf0000UL)               /*!< LPSC (Bitfield-Mask: 0x0f)                            */
/* ========================================================  CH0CNT  ========================================================= */
#define IPWM_CH0CNT_COUNT_Pos             (0UL)                     /*!< COUNT (Bit 0)                                         */
#define IPWM_CH0CNT_COUNT_Msk             (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH1CNT  ========================================================= */
#define IPWM_CH1CNT_COUNT_Pos             (0UL)                     /*!< COUNT (Bit 0)                                         */
#define IPWM_CH1CNT_COUNT_Msk             (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH2CNT  ========================================================= */
#define IPWM_CH2CNT_COUNT_Pos             (0UL)                     /*!< COUNT (Bit 0)                                         */
#define IPWM_CH2CNT_COUNT_Msk             (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH3CNT  ========================================================= */
#define IPWM_CH3CNT_COUNT_Pos             (0UL)                     /*!< COUNT (Bit 0)                                         */
#define IPWM_CH3CNT_COUNT_Msk             (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CH0MOD  ========================================================= */
#define IPWM_CH0MOD_MOD_Pos               (0UL)                     /*!< MOD (Bit 0)                                           */
#define IPWM_CH0MOD_MOD_Msk               (0xffffUL)                /*!< MOD (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH1MOD  ========================================================= */
#define IPWM_CH1MOD_MOD_Pos               (0UL)                     /*!< MOD (Bit 0)                                           */
#define IPWM_CH1MOD_MOD_Msk               (0xffffUL)                /*!< MOD (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH2MOD  ========================================================= */
#define IPWM_CH2MOD_MOD_Pos               (0UL)                     /*!< MOD (Bit 0)                                           */
#define IPWM_CH2MOD_MOD_Msk               (0xffffUL)                /*!< MOD (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH3MOD  ========================================================= */
#define IPWM_CH3MOD_MOD_Pos               (0UL)                     /*!< MOD (Bit 0)                                           */
#define IPWM_CH3MOD_MOD_Msk               (0xffffUL)                /*!< MOD (Bitfield-Mask: 0xffff)                           */
/* =======================================================  CH0CNTIN  ======================================================== */
#define IPWM_CH0CNTIN_CNTIN_Pos           (0UL)                     /*!< CNTIN (Bit 0)                                         */
#define IPWM_CH0CNTIN_CNTIN_Msk           (0xffffUL)                /*!< CNTIN (Bitfield-Mask: 0xffff)                         */
/* =======================================================  CH1CNTIN  ======================================================== */
#define IPWM_CH1CNTIN_CNTIN_Pos           (0UL)                     /*!< CNTIN (Bit 0)                                         */
#define IPWM_CH1CNTIN_CNTIN_Msk           (0xffffUL)                /*!< CNTIN (Bitfield-Mask: 0xffff)                         */
/* =======================================================  CH2CNTIN  ======================================================== */
#define IPWM_CH2CNTIN_CNTIN_Pos           (0UL)                     /*!< CNTIN (Bit 0)                                         */
#define IPWM_CH2CNTIN_CNTIN_Msk           (0xffffUL)                /*!< CNTIN (Bitfield-Mask: 0xffff)                         */
/* =======================================================  CH3CNTIN  ======================================================== */
#define IPWM_CH3CNTIN_CNTIN_Pos           (0UL)                     /*!< CNTIN (Bit 0)                                         */
#define IPWM_CH3CNTIN_CNTIN_Msk           (0xffffUL)                /*!< CNTIN (Bitfield-Mask: 0xffff)                         */
/* =========================================================  CH0SC  ========================================================= */
#define IPWM_CH0SC_ICaRST_Pos             (0UL)                     /*!< ICaRST (Bit 0)                                        */
#define IPWM_CH0SC_ICaRST_Msk             (0x1UL)                   /*!< ICaRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH0SC_ICbRST_Pos             (1UL)                     /*!< ICbRST (Bit 1)                                        */
#define IPWM_CH0SC_ICbRST_Msk             (0x2UL)                   /*!< ICbRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH0SC_DIRa_Pos               (2UL)                     /*!< DIRa (Bit 2)                                          */
#define IPWM_CH0SC_DIRa_Msk               (0x4UL)                   /*!< DIRa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH0SC_DIRb_Pos               (3UL)                     /*!< DIRb (Bit 3)                                          */
#define IPWM_CH0SC_DIRb_Msk               (0x8UL)                   /*!< DIRb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH0SC_ELSa_Pos               (4UL)                     /*!< ELSa (Bit 4)                                          */
#define IPWM_CH0SC_ELSa_Msk               (0x10UL)                  /*!< ELSa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH0SC_ELSb_Pos               (6UL)                     /*!< ELSb (Bit 6)                                          */
#define IPWM_CH0SC_ELSb_Msk               (0x40UL)                  /*!< ELSb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH0SC_MSEL_Pos               (8UL)                     /*!< MSEL (Bit 8)                                          */
#define IPWM_CH0SC_MSEL_Msk               (0x300UL)                 /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define IPWM_CH0SC_CHFaPSC_Pos            (12UL)                    /*!< CHFaPSC (Bit 12)                                      */
#define IPWM_CH0SC_CHFaPSC_Msk            (0x3000UL)                /*!< CHFaPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH0SC_CHFbPSC_Pos            (14UL)                    /*!< CHFbPSC (Bit 14)                                      */
#define IPWM_CH0SC_CHFbPSC_Msk            (0xc000UL)                /*!< CHFbPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH0SC_CHIEa_Pos              (16UL)                    /*!< CHIEa (Bit 16)                                        */
#define IPWM_CH0SC_CHIEa_Msk              (0x10000UL)               /*!< CHIEa (Bitfield-Mask: 0x01)                           */
#define IPWM_CH0SC_CHIEb_Pos              (17UL)                    /*!< CHIEb (Bit 17)                                        */
#define IPWM_CH0SC_CHIEb_Msk              (0x20000UL)               /*!< CHIEb (Bitfield-Mask: 0x01)                           */
#define IPWM_CH0SC_CHFa_Pos               (18UL)                    /*!< CHFa (Bit 18)                                         */
#define IPWM_CH0SC_CHFa_Msk               (0x40000UL)               /*!< CHFa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH0SC_CHFb_Pos               (19UL)                    /*!< CHFb (Bit 19)                                         */
#define IPWM_CH0SC_CHFb_Msk               (0x80000UL)               /*!< CHFb (Bitfield-Mask: 0x01)                            */
/* =========================================================  CH1SC  ========================================================= */
#define IPWM_CH1SC_ICaRST_Pos             (0UL)                     /*!< ICaRST (Bit 0)                                        */
#define IPWM_CH1SC_ICaRST_Msk             (0x1UL)                   /*!< ICaRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH1SC_ICbRST_Pos             (1UL)                     /*!< ICbRST (Bit 1)                                        */
#define IPWM_CH1SC_ICbRST_Msk             (0x2UL)                   /*!< ICbRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH1SC_DIRa_Pos               (2UL)                     /*!< DIRa (Bit 2)                                          */
#define IPWM_CH1SC_DIRa_Msk               (0x4UL)                   /*!< DIRa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH1SC_DIRb_Pos               (3UL)                     /*!< DIRb (Bit 3)                                          */
#define IPWM_CH1SC_DIRb_Msk               (0x8UL)                   /*!< DIRb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH1SC_ELSa_Pos               (4UL)                     /*!< ELSa (Bit 4)                                          */
#define IPWM_CH1SC_ELSa_Msk               (0x10UL)                  /*!< ELSa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH1SC_ELSb_Pos               (6UL)                     /*!< ELSb (Bit 6)                                          */
#define IPWM_CH1SC_ELSb_Msk               (0x40UL)                  /*!< ELSb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH1SC_MSEL_Pos               (8UL)                     /*!< MSEL (Bit 8)                                          */
#define IPWM_CH1SC_MSEL_Msk               (0x300UL)                 /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define IPWM_CH1SC_CHFaPSC_Pos            (12UL)                    /*!< CHFaPSC (Bit 12)                                      */
#define IPWM_CH1SC_CHFaPSC_Msk            (0x3000UL)                /*!< CHFaPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH1SC_CHFbPSC_Pos            (14UL)                    /*!< CHFbPSC (Bit 14)                                      */
#define IPWM_CH1SC_CHFbPSC_Msk            (0xc000UL)                /*!< CHFbPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH1SC_CHIEa_Pos              (16UL)                    /*!< CHIEa (Bit 16)                                        */
#define IPWM_CH1SC_CHIEa_Msk              (0x10000UL)               /*!< CHIEa (Bitfield-Mask: 0x01)                           */
#define IPWM_CH1SC_CHIEb_Pos              (17UL)                    /*!< CHIEb (Bit 17)                                        */
#define IPWM_CH1SC_CHIEb_Msk              (0x20000UL)               /*!< CHIEb (Bitfield-Mask: 0x01)                           */
#define IPWM_CH1SC_CHFa_Pos               (18UL)                    /*!< CHFa (Bit 18)                                         */
#define IPWM_CH1SC_CHFa_Msk               (0x40000UL)               /*!< CHFa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH1SC_CHFb_Pos               (19UL)                    /*!< CHFb (Bit 19)                                         */
#define IPWM_CH1SC_CHFb_Msk               (0x80000UL)               /*!< CHFb (Bitfield-Mask: 0x01)                            */
/* =========================================================  CH2SC  ========================================================= */
#define IPWM_CH2SC_ICaRST_Pos             (0UL)                     /*!< ICaRST (Bit 0)                                        */
#define IPWM_CH2SC_ICaRST_Msk             (0x1UL)                   /*!< ICaRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH2SC_ICbRST_Pos             (1UL)                     /*!< ICbRST (Bit 1)                                        */
#define IPWM_CH2SC_ICbRST_Msk             (0x2UL)                   /*!< ICbRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH2SC_DIRa_Pos               (2UL)                     /*!< DIRa (Bit 2)                                          */
#define IPWM_CH2SC_DIRa_Msk               (0x4UL)                   /*!< DIRa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH2SC_DIRb_Pos               (3UL)                     /*!< DIRb (Bit 3)                                          */
#define IPWM_CH2SC_DIRb_Msk               (0x8UL)                   /*!< DIRb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH2SC_ELSa_Pos               (4UL)                     /*!< ELSa (Bit 4)                                          */
#define IPWM_CH2SC_ELSa_Msk               (0x10UL)                  /*!< ELSa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH2SC_ELSb_Pos               (6UL)                     /*!< ELSb (Bit 6)                                          */
#define IPWM_CH2SC_ELSb_Msk               (0x40UL)                  /*!< ELSb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH2SC_MSEL_Pos               (8UL)                     /*!< MSEL (Bit 8)                                          */
#define IPWM_CH2SC_MSEL_Msk               (0x300UL)                 /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define IPWM_CH2SC_CHFaPSC_Pos            (12UL)                    /*!< CHFaPSC (Bit 12)                                      */
#define IPWM_CH2SC_CHFaPSC_Msk            (0x3000UL)                /*!< CHFaPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH2SC_CHFbPSC_Pos            (14UL)                    /*!< CHFbPSC (Bit 14)                                      */
#define IPWM_CH2SC_CHFbPSC_Msk            (0xc000UL)                /*!< CHFbPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH2SC_CHIEa_Pos              (16UL)                    /*!< CHIEa (Bit 16)                                        */
#define IPWM_CH2SC_CHIEa_Msk              (0x10000UL)               /*!< CHIEa (Bitfield-Mask: 0x01)                           */
#define IPWM_CH2SC_CHIEb_Pos              (17UL)                    /*!< CHIEb (Bit 17)                                        */
#define IPWM_CH2SC_CHIEb_Msk              (0x20000UL)               /*!< CHIEb (Bitfield-Mask: 0x01)                           */
#define IPWM_CH2SC_CHFa_Pos               (18UL)                    /*!< CHFa (Bit 18)                                         */
#define IPWM_CH2SC_CHFa_Msk               (0x40000UL)               /*!< CHFa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH2SC_CHFb_Pos               (19UL)                    /*!< CHFb (Bit 19)                                         */
#define IPWM_CH2SC_CHFb_Msk               (0x80000UL)               /*!< CHFb (Bitfield-Mask: 0x01)                            */
/* =========================================================  CH3SC  ========================================================= */
#define IPWM_CH3SC_ICaRST_Pos             (0UL)                     /*!< ICaRST (Bit 0)                                        */
#define IPWM_CH3SC_ICaRST_Msk             (0x1UL)                   /*!< ICaRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH3SC_ICbRST_Pos             (1UL)                     /*!< ICbRST (Bit 1)                                        */
#define IPWM_CH3SC_ICbRST_Msk             (0x2UL)                   /*!< ICbRST (Bitfield-Mask: 0x01)                          */
#define IPWM_CH3SC_DIRa_Pos               (2UL)                     /*!< DIRa (Bit 2)                                          */
#define IPWM_CH3SC_DIRa_Msk               (0x4UL)                   /*!< DIRa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH3SC_DIRb_Pos               (3UL)                     /*!< DIRb (Bit 3)                                          */
#define IPWM_CH3SC_DIRb_Msk               (0x8UL)                   /*!< DIRb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH3SC_ELSa_Pos               (4UL)                     /*!< ELSa (Bit 4)                                          */
#define IPWM_CH3SC_ELSa_Msk               (0x10UL)                  /*!< ELSa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH3SC_ELSb_Pos               (6UL)                     /*!< ELSb (Bit 6)                                          */
#define IPWM_CH3SC_ELSb_Msk               (0x40UL)                  /*!< ELSb (Bitfield-Mask: 0x01)                            */
#define IPWM_CH3SC_MSEL_Pos               (8UL)                     /*!< MSEL (Bit 8)                                          */
#define IPWM_CH3SC_MSEL_Msk               (0x300UL)                 /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define IPWM_CH3SC_CHFaPSC_Pos            (12UL)                    /*!< CHFaPSC (Bit 12)                                      */
#define IPWM_CH3SC_CHFaPSC_Msk            (0x3000UL)                /*!< CHFaPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH3SC_CHFbPSC_Pos            (14UL)                    /*!< CHFbPSC (Bit 14)                                      */
#define IPWM_CH3SC_CHFbPSC_Msk            (0xc000UL)                /*!< CHFbPSC (Bitfield-Mask: 0x03)                         */
#define IPWM_CH3SC_CHIEa_Pos              (16UL)                    /*!< CHIEa (Bit 16)                                        */
#define IPWM_CH3SC_CHIEa_Msk              (0x10000UL)               /*!< CHIEa (Bitfield-Mask: 0x01)                           */
#define IPWM_CH3SC_CHIEb_Pos              (17UL)                    /*!< CHIEb (Bit 17)                                        */
#define IPWM_CH3SC_CHIEb_Msk              (0x20000UL)               /*!< CHIEb (Bitfield-Mask: 0x01)                           */
#define IPWM_CH3SC_CHFa_Pos               (18UL)                    /*!< CHFa (Bit 18)                                         */
#define IPWM_CH3SC_CHFa_Msk               (0x40000UL)               /*!< CHFa (Bitfield-Mask: 0x01)                            */
#define IPWM_CH3SC_CHFb_Pos               (19UL)                    /*!< CHFb (Bit 19)                                         */
#define IPWM_CH3SC_CHFb_Msk               (0x80000UL)               /*!< CHFb (Bitfield-Mask: 0x01)                            */
/* ========================================================  CH0CVa  ========================================================= */
#define IPWM_CH0CVa_CVa_Pos               (0UL)                     /*!< CVa (Bit 0)                                           */
#define IPWM_CH0CVa_CVa_Msk               (0xffffUL)                /*!< CVa (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH1CVa  ========================================================= */
#define IPWM_CH1CVa_CVa_Pos               (0UL)                     /*!< CVa (Bit 0)                                           */
#define IPWM_CH1CVa_CVa_Msk               (0xffffUL)                /*!< CVa (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH2CVa  ========================================================= */
#define IPWM_CH2CVa_CVa_Pos               (0UL)                     /*!< CVa (Bit 0)                                           */
#define IPWM_CH2CVa_CVa_Msk               (0xffffUL)                /*!< CVa (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH3CVa  ========================================================= */
#define IPWM_CH3CVa_CVa_Pos               (0UL)                     /*!< CVa (Bit 0)                                           */
#define IPWM_CH3CVa_CVa_Msk               (0xffffUL)                /*!< CVa (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH0CVb  ========================================================= */
#define IPWM_CH0CVb_CVb_Pos               (0UL)                     /*!< CVb (Bit 0)                                           */
#define IPWM_CH0CVb_CVb_Msk               (0xffffUL)                /*!< CVb (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH1CVb  ========================================================= */
#define IPWM_CH1CVb_CVb_Pos               (0UL)                     /*!< CVb (Bit 0)                                           */
#define IPWM_CH1CVb_CVb_Msk               (0xffffUL)                /*!< CVb (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH2CVb  ========================================================= */
#define IPWM_CH2CVb_CVb_Pos               (0UL)                     /*!< CVb (Bit 0)                                           */
#define IPWM_CH2CVb_CVb_Msk               (0xffffUL)                /*!< CVb (Bitfield-Mask: 0xffff)                           */
/* ========================================================  CH3CVb  ========================================================= */
#define IPWM_CH3CVb_CVb_Pos               (0UL)                     /*!< CVb (Bit 0)                                           */
#define IPWM_CH3CVb_CVb_Msk               (0xffffUL)                /*!< CVb (Bitfield-Mask: 0xffff)                           */
/* ========================================================  STATUS  ========================================================= */
#define IPWM_STATUS_CH0Fa_Pos             (0UL)                     /*!< CH0Fa (Bit 0)                                         */
#define IPWM_STATUS_CH0Fa_Msk             (0x1UL)                   /*!< CH0Fa (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH0Fb_Pos             (1UL)                     /*!< CH0Fb (Bit 1)                                         */
#define IPWM_STATUS_CH0Fb_Msk             (0x2UL)                   /*!< CH0Fb (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH1Fa_Pos             (2UL)                     /*!< CH1Fa (Bit 2)                                         */
#define IPWM_STATUS_CH1Fa_Msk             (0x4UL)                   /*!< CH1Fa (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH1Fb_Pos             (3UL)                     /*!< CH1Fb (Bit 3)                                         */
#define IPWM_STATUS_CH1Fb_Msk             (0x8UL)                   /*!< CH1Fb (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH2Fa_Pos             (4UL)                     /*!< CH2Fa (Bit 4)                                         */
#define IPWM_STATUS_CH2Fa_Msk             (0x10UL)                  /*!< CH2Fa (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH2Fb_Pos             (5UL)                     /*!< CH2Fb (Bit 5)                                         */
#define IPWM_STATUS_CH2Fb_Msk             (0x20UL)                  /*!< CH2Fb (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH3Fa_Pos             (6UL)                     /*!< CH3Fa (Bit 6)                                         */
#define IPWM_STATUS_CH3Fa_Msk             (0x40UL)                  /*!< CH3Fa (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH3Fb_Pos             (7UL)                     /*!< CH3Fb (Bit 7)                                         */
#define IPWM_STATUS_CH3Fb_Msk             (0x80UL)                  /*!< CH3Fb (Bitfield-Mask: 0x01)                           */
#define IPWM_STATUS_CH0LVL_Pos            (8UL)                     /*!< CH0LVL (Bit 8)                                        */
#define IPWM_STATUS_CH0LVL_Msk            (0x100UL)                 /*!< CH0LVL (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH1LVL_Pos            (9UL)                     /*!< CH1LVL (Bit 9)                                        */
#define IPWM_STATUS_CH1LVL_Msk            (0x200UL)                 /*!< CH1LVL (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH2LVL_Pos            (10UL)                    /*!< CH2LVL (Bit 10)                                       */
#define IPWM_STATUS_CH2LVL_Msk            (0x400UL)                 /*!< CH2LVL (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH3LVL_Pos            (11UL)                    /*!< CH3LVL (Bit 11)                                       */
#define IPWM_STATUS_CH3LVL_Msk            (0x800UL)                 /*!< CH3LVL (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH0COF_Pos            (16UL)                    /*!< CH0COF (Bit 16)                                       */
#define IPWM_STATUS_CH0COF_Msk            (0x10000UL)               /*!< CH0COF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH1COF_Pos            (17UL)                    /*!< CH1COF (Bit 17)                                       */
#define IPWM_STATUS_CH1COF_Msk            (0x20000UL)               /*!< CH1COF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH2COF_Pos            (18UL)                    /*!< CH2COF (Bit 18)                                       */
#define IPWM_STATUS_CH2COF_Msk            (0x40000UL)               /*!< CH2COF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH3COF_Pos            (19UL)                    /*!< CH3COF (Bit 19)                                       */
#define IPWM_STATUS_CH3COF_Msk            (0x80000UL)               /*!< CH3COF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH0CUF_Pos            (20UL)                    /*!< CH0CUF (Bit 20)                                       */
#define IPWM_STATUS_CH0CUF_Msk            (0x100000UL)              /*!< CH0CUF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH1CUF_Pos            (21UL)                    /*!< CH1CUF (Bit 21)                                       */
#define IPWM_STATUS_CH1CUF_Msk            (0x200000UL)              /*!< CH1CUF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH2CUF_Pos            (22UL)                    /*!< CH2CUF (Bit 22)                                       */
#define IPWM_STATUS_CH2CUF_Msk            (0x400000UL)              /*!< CH2CUF (Bitfield-Mask: 0x01)                          */
#define IPWM_STATUS_CH3CUF_Pos            (23UL)                    /*!< CH3CUF (Bit 23)                                       */
#define IPWM_STATUS_CH3CUF_Msk            (0x800000UL)              /*!< CH3CUF (Bitfield-Mask: 0x01)                          */
/* =========================================================  MODE  ========================================================== */
#define IPWM_MODE_SYNCEN0_Pos             (0UL)                     /*!< SYNCEN0 (Bit 0)                                       */
#define IPWM_MODE_SYNCEN0_Msk             (0x1UL)                   /*!< SYNCEN0 (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_SYNCEN1_Pos             (1UL)                     /*!< SYNCEN1 (Bit 1)                                       */
#define IPWM_MODE_SYNCEN1_Msk             (0x2UL)                   /*!< SYNCEN1 (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_SYNCEN2_Pos             (2UL)                     /*!< SYNCEN2 (Bit 2)                                       */
#define IPWM_MODE_SYNCEN2_Msk             (0x4UL)                   /*!< SYNCEN2 (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_SYNCEN3_Pos             (3UL)                     /*!< SYNCEN3 (Bit 3)                                       */
#define IPWM_MODE_SYNCEN3_Msk             (0x8UL)                   /*!< SYNCEN3 (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_WPDIS_Pos               (4UL)                     /*!< WPDIS (Bit 4)                                         */
#define IPWM_MODE_WPDIS_Msk               (0x10UL)                  /*!< WPDIS (Bitfield-Mask: 0x01)                           */
#define IPWM_MODE_BUFFRD_Pos              (7UL)                     /*!< BUFFRD (Bit 7)                                        */
#define IPWM_MODE_BUFFRD_Msk              (0x80UL)                  /*!< BUFFRD (Bitfield-Mask: 0x01)                          */
#define IPWM_MODE_CH0INIT_Pos             (8UL)                     /*!< CH0INIT (Bit 8)                                       */
#define IPWM_MODE_CH0INIT_Msk             (0x100UL)                 /*!< CH0INIT (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_CH1INIT_Pos             (9UL)                     /*!< CH1INIT (Bit 9)                                       */
#define IPWM_MODE_CH1INIT_Msk             (0x200UL)                 /*!< CH1INIT (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_CH2INIT_Pos             (10UL)                    /*!< CH2INIT (Bit 10)                                      */
#define IPWM_MODE_CH2INIT_Msk             (0x400UL)                 /*!< CH2INIT (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_CH3INIT_Pos             (11UL)                    /*!< CH3INIT (Bit 11)                                      */
#define IPWM_MODE_CH3INIT_Msk             (0x800UL)                 /*!< CH3INIT (Bitfield-Mask: 0x01)                         */
#define IPWM_MODE_HALL_Pos                (12UL)                    /*!< HALL (Bit 12)                                         */
#define IPWM_MODE_HALL_Msk                (0x1000UL)                /*!< HALL (Bitfield-Mask: 0x01)                            */
/* =========================================================  SYNC  ========================================================== */
#define IPWM_SYNC_CNT0MIN_Pos             (0UL)                     /*!< CNT0MIN (Bit 0)                                       */
#define IPWM_SYNC_CNT0MIN_Msk             (0x1UL)                   /*!< CNT0MIN (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT0MAX_Pos             (1UL)                     /*!< CNT0MAX (Bit 1)                                       */
#define IPWM_SYNC_CNT0MAX_Msk             (0x2UL)                   /*!< CNT0MAX (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT1MIN_Pos             (2UL)                     /*!< CNT1MIN (Bit 2)                                       */
#define IPWM_SYNC_CNT1MIN_Msk             (0x4UL)                   /*!< CNT1MIN (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT1MAX_Pos             (3UL)                     /*!< CNT1MAX (Bit 3)                                       */
#define IPWM_SYNC_CNT1MAX_Msk             (0x8UL)                   /*!< CNT1MAX (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT2MIN_Pos             (4UL)                     /*!< CNT2MIN (Bit 4)                                       */
#define IPWM_SYNC_CNT2MIN_Msk             (0x10UL)                  /*!< CNT2MIN (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT2MAX_Pos             (5UL)                     /*!< CNT2MAX (Bit 5)                                       */
#define IPWM_SYNC_CNT2MAX_Msk             (0x20UL)                  /*!< CNT2MAX (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT3MIN_Pos             (6UL)                     /*!< CNT3MIN (Bit 6)                                       */
#define IPWM_SYNC_CNT3MIN_Msk             (0x40UL)                  /*!< CNT3MIN (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CNT3MAX_Pos             (7UL)                     /*!< CNT3MAX (Bit 7)                                       */
#define IPWM_SYNC_CNT3MAX_Msk             (0x80UL)                  /*!< CNT3MAX (Bitfield-Mask: 0x01)                         */
#define IPWM_SYNC_CH0SWSYNC_Pos           (8UL)                     /*!< CH0SWSYNC (Bit 8)                                     */
#define IPWM_SYNC_CH0SWSYNC_Msk           (0x100UL)                 /*!< CH0SWSYNC (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNC_CH1SWSYNC_Pos           (9UL)                     /*!< CH1SWSYNC (Bit 9)                                     */
#define IPWM_SYNC_CH1SWSYNC_Msk           (0x200UL)                 /*!< CH1SWSYNC (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNC_CH2SWSYNC_Pos           (10UL)                    /*!< CH2SWSYNC (Bit 10)                                    */
#define IPWM_SYNC_CH2SWSYNC_Msk           (0x400UL)                 /*!< CH2SWSYNC (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNC_CH3SWSYNC_Pos           (11UL)                    /*!< CH3SWSYNC (Bit 11)                                    */
#define IPWM_SYNC_CH3SWSYNC_Msk           (0x800UL)                 /*!< CH3SWSYNC (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNC_WPEN_Pos                (14UL)                    /*!< WPEN (Bit 14)                                         */
#define IPWM_SYNC_WPEN_Msk                (0x4000UL)                /*!< WPEN (Bitfield-Mask: 0x01)                            */
/* ========================================================  OUTINIT  ======================================================== */
#define IPWM_OUTINIT_CH0OI_Pos            (0UL)                     /*!< CH0OI (Bit 0)                                         */
#define IPWM_OUTINIT_CH0OI_Msk            (0x1UL)                   /*!< CH0OI (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTINIT_CH1OI_Pos            (1UL)                     /*!< CH1OI (Bit 1)                                         */
#define IPWM_OUTINIT_CH1OI_Msk            (0x2UL)                   /*!< CH1OI (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTINIT_CH2OI_Pos            (2UL)                     /*!< CH2OI (Bit 2)                                         */
#define IPWM_OUTINIT_CH2OI_Msk            (0x4UL)                   /*!< CH2OI (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTINIT_CH3OI_Pos            (3UL)                     /*!< CH3OI (Bit 3)                                         */
#define IPWM_OUTINIT_CH3OI_Msk            (0x8UL)                   /*!< CH3OI (Bitfield-Mask: 0x01)                           */
/* ========================================================  OUTMAS   ======================================================== */
#define IPWM_OUTMASK_CH0OM_Pos            (0UL)                     /*!< CH0OM (Bit 0)                                         */
#define IPWM_OUTMASK_CH0OM_Msk            (0x1UL)                   /*!< CH0OM (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTMASK_CH1OM_Pos            (1UL)                     /*!< CH1OM (Bit 1)                                         */
#define IPWM_OUTMASK_CH1OM_Msk            (0x2UL)                   /*!< CH1OM (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTMASK_CH2OM_Pos            (2UL)                     /*!< CH2OM (Bit 2)                                         */
#define IPWM_OUTMASK_CH2OM_Msk            (0x4UL)                   /*!< CH2OM (Bitfield-Mask: 0x01)                           */
#define IPWM_OUTMASK_CH3OM_Pos            (3UL)                     /*!< CH3OM (Bit 3)                                         */
#define IPWM_OUTMASK_CH3OM_Msk            (0x8UL)                   /*!< CH3OM (Bitfield-Mask: 0x01)                           */
/* ========================================================  SWOCTRL  ======================================================== */
#define IPWM_SWOCTRL_CH0OC_Pos            (0UL)                     /*!< CH0OC (Bit 0)                                         */
#define IPWM_SWOCTRL_CH0OC_Msk            (0x1UL)                   /*!< CH0OC (Bitfield-Mask: 0x01)                           */
#define IPWM_SWOCTRL_CH1OC_Pos            (1UL)                     /*!< CH1OC (Bit 1)                                         */
#define IPWM_SWOCTRL_CH1OC_Msk            (0x2UL)                   /*!< CH1OC (Bitfield-Mask: 0x01)                           */
#define IPWM_SWOCTRL_CH2OC_Pos            (2UL)                     /*!< CH2OC (Bit 2)                                         */
#define IPWM_SWOCTRL_CH2OC_Msk            (0x4UL)                   /*!< CH2OC (Bitfield-Mask: 0x01)                           */
#define IPWM_SWOCTRL_CH3OC_Pos            (3UL)                     /*!< CH3OC (Bit 3)                                         */
#define IPWM_SWOCTRL_CH3OC_Msk            (0x8UL)                   /*!< CH3OC (Bitfield-Mask: 0x01)                           */
#define IPWM_SWOCTRL_CH0OCV_Pos           (4UL)                     /*!< CH0OCV (Bit 4)                                        */
#define IPWM_SWOCTRL_CH0OCV_Msk           (0x10UL)                  /*!< CH0OCV (Bitfield-Mask: 0x01)                          */
#define IPWM_SWOCTRL_CH1OCV_Pos           (5UL)                     /*!< CH1OCV (Bit 5)                                        */
#define IPWM_SWOCTRL_CH1OCV_Msk           (0x20UL)                  /*!< CH1OCV (Bitfield-Mask: 0x01)                          */
#define IPWM_SWOCTRL_CH2OCV_Pos           (6UL)                     /*!< CH2OCV (Bit 6)                                        */
#define IPWM_SWOCTRL_CH2OCV_Msk           (0x40UL)                  /*!< CH2OCV (Bitfield-Mask: 0x01)                          */
#define IPWM_SWOCTRL_CH3OCV_Pos           (7UL)                     /*!< CH3OCV (Bit 7)                                        */
#define IPWM_SWOCTRL_CH3OCV_Msk           (0x80UL)                  /*!< CH3OCV (Bitfield-Mask: 0x01)                          */
/* ========================================================  EXTTRIG  ======================================================== */
#define IPWM_EXTTRIG_CH0MINTRIG_Pos       (0UL)                     /*!< CH0MINTRIG (Bit 0)                                    */
#define IPWM_EXTTRIG_CH0MINTRIG_Msk       (0x1UL)                   /*!< CH0MINTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH1MINTRIG_Pos       (1UL)                     /*!< CH1MINTRIG (Bit 1)                                    */
#define IPWM_EXTTRIG_CH1MINTRIG_Msk       (0x2UL)                   /*!< CH1MINTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH2MINTRIG_Pos       (2UL)                     /*!< CH2MINTRIG (Bit 2)                                    */
#define IPWM_EXTTRIG_CH2MINTRIG_Msk       (0x4UL)                   /*!< CH2MINTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH3MINTRIG_Pos       (3UL)                     /*!< CH3MINTRIG (Bit 3)                                    */
#define IPWM_EXTTRIG_CH3MINTRIG_Msk       (0x8UL)                   /*!< CH3MINTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH0MAXTRIG_Pos       (4UL)                     /*!< CH0MAXTRIG (Bit 4)                                    */
#define IPWM_EXTTRIG_CH0MAXTRIG_Msk       (0x10UL)                  /*!< CH0MAXTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH1MAXTRIG_Pos       (5UL)                     /*!< CH1MAXTRIG (Bit 5)                                    */
#define IPWM_EXTTRIG_CH1MAXTRIG_Msk       (0x20UL)                  /*!< CH1MAXTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH2MAXTRIG_Pos       (6UL)                     /*!< CH2MAXTRIG (Bit 6)                                    */
#define IPWM_EXTTRIG_CH2MAXTRIG_Msk       (0x40UL)                  /*!< CH2MAXTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH3MAXTRIG_Pos       (7UL)                     /*!< CH3MAXTRIG (Bit 7)                                    */
#define IPWM_EXTTRIG_CH3MAXTRIG_Msk       (0x80UL)                  /*!< CH3MAXTRIG (Bitfield-Mask: 0x01)                      */
#define IPWM_EXTTRIG_CH0MATCHTRIGa_Pos    (8UL)                     /*!< CH0MATCHTRIGa (Bit 8)                                 */
#define IPWM_EXTTRIG_CH0MATCHTRIGa_Msk    (0x100UL)                 /*!< CH0MATCHTRIGa (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH0MATCHTRIGb_Pos    (9UL)                     /*!< CH0MATCHTRIGb (Bit 9)                                 */
#define IPWM_EXTTRIG_CH0MATCHTRIGb_Msk    (0x200UL)                 /*!< CH0MATCHTRIGb (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH1MATCHTRIGa_Pos    (10UL)                    /*!< CH1MATCHTRIGa (Bit 10)                                */
#define IPWM_EXTTRIG_CH1MATCHTRIGa_Msk    (0x400UL)                 /*!< CH1MATCHTRIGa (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH1MATCHTRIGb_Pos    (11UL)                    /*!< CH1MATCHTRIGb (Bit 11)                                */
#define IPWM_EXTTRIG_CH1MATCHTRIGb_Msk    (0x800UL)                 /*!< CH1MATCHTRIGb (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH2MATCHTRIGa_Pos    (12UL)                    /*!< CH2MATCHTRIGa (Bit 12)                                */
#define IPWM_EXTTRIG_CH2MATCHTRIGa_Msk    (0x1000UL)                /*!< CH2MATCHTRIGa (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH2MATCHTRIGb_Pos    (13UL)                    /*!< CH2MATCHTRIGb (Bit 13)                                */
#define IPWM_EXTTRIG_CH2MATCHTRIGb_Msk    (0x2000UL)                /*!< CH2MATCHTRIGb (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH3MATCHTRIGa_Pos    (14UL)                    /*!< CH3MATCHTRIGa (Bit 14)                                */
#define IPWM_EXTTRIG_CH3MATCHTRIGa_Msk    (0x4000UL)                /*!< CH3MATCHTRIGa (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_CH3MATCHTRIGb_Pos    (15UL)                    /*!< CH3MATCHTRIGb (Bit 15)                                */
#define IPWM_EXTTRIG_CH3MATCHTRIGb_Msk    (0x8000UL)                /*!< CH3MATCHTRIGb (Bitfield-Mask: 0x01)                   */
#define IPWM_EXTTRIG_TRIGPSC_Pos          (16UL)                    /*!< TRIGPSC (Bit 16)                                      */
#define IPWM_EXTTRIG_TRIGPSC_Msk          (0x70000UL)               /*!< TRIGPSC (Bitfield-Mask: 0x07)                         */
/* ========================================================  FILTER  ========================================================= */
#define IPWM_FILTER_CH0FVAL_Pos           (0UL)                     /*!< CH0FVAL (Bit 0)                                       */
#define IPWM_FILTER_CH0FVAL_Msk           (0xfUL)                   /*!< CH0FVAL (Bitfield-Mask: 0x0f)                         */
#define IPWM_FILTER_CH1FVAL_Pos           (4UL)                     /*!< CH1FVAL (Bit 4)                                       */
#define IPWM_FILTER_CH1FVAL_Msk           (0xf0UL)                  /*!< CH1FVAL (Bitfield-Mask: 0x0f)                         */
#define IPWM_FILTER_CH2FVAL_Pos           (8UL)                     /*!< CH2FVAL (Bit 8)                                       */
#define IPWM_FILTER_CH2FVAL_Msk           (0xf00UL)                 /*!< CH2FVAL (Bitfield-Mask: 0x0f)                         */
#define IPWM_FILTER_CH3FVAL_Pos           (12UL)                    /*!< CH3FVAL (Bit 12)                                      */
#define IPWM_FILTER_CH3FVAL_Msk           (0xf000UL)                /*!< CH3FVAL (Bitfield-Mask: 0x0f)                         */
#define IPWM_FILTER_FILTPSC_Pos           (16UL)                    /*!< FILTPSC (Bit 16)                                      */
#define IPWM_FILTER_FILTPSC_Msk           (0xf0000UL)               /*!< FILTPSC (Bitfield-Mask: 0x0f)                         */
/* ========================================================  QDCTRL  ========================================================= */
#define IPWM_QDCTRL_QUADEN_Pos            (0UL)                     /*!< QUADEN (Bit 0)                                        */
#define IPWM_QDCTRL_QUADEN_Msk            (0x1UL)                   /*!< QUADEN (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_QUADIR_Pos            (1UL)                     /*!< QUADIR (Bit 1)                                        */
#define IPWM_QDCTRL_QUADIR_Msk            (0x2UL)                   /*!< QUADIR (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_QUADMODE_Pos          (3UL)                     /*!< QUADMODE (Bit 3)                                      */
#define IPWM_QDCTRL_QUADMODE_Msk          (0x8UL)                   /*!< QUADMODE (Bitfield-Mask: 0x01)                        */
#define IPWM_QDCTRL_PHAPOL_Pos            (4UL)                     /*!< PHAPOL (Bit 4)                                        */
#define IPWM_QDCTRL_PHAPOL_Msk            (0x10UL)                  /*!< PHAPOL (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_PHBPOL_Pos            (5UL)                     /*!< PHBPOL (Bit 5)                                        */
#define IPWM_QDCTRL_PHBPOL_Msk            (0x20UL)                  /*!< PHBPOL (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_PHZPOL_Pos            (6UL)                     /*!< PHZPOL (Bit 6)                                        */
#define IPWM_QDCTRL_PHZPOL_Msk            (0x40UL)                  /*!< PHZPOL (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_PHZRST_Pos            (7UL)                     /*!< PHZRST (Bit 7)                                        */
#define IPWM_QDCTRL_PHZRST_Msk            (0x80UL)                  /*!< PHZRST (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_PHZSTS_Pos            (8UL)                     /*!< PHZSTS (Bit 8)                                        */
#define IPWM_QDCTRL_PHZSTS_Msk            (0x100UL)                 /*!< PHZSTS (Bitfield-Mask: 0x01)                          */
#define IPWM_QDCTRL_PHZIE_Pos             (9UL)                     /*!< PHZIE (Bit 9)                                         */
#define IPWM_QDCTRL_PHZIE_Msk             (0x200UL)                 /*!< PHZIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  POL  ========================================================== */
#define IPWM_POL_CH0POL_Pos               (0UL)                     /*!< CH0POL (Bit 0)                                        */
#define IPWM_POL_CH0POL_Msk               (0x1UL)                   /*!< CH0POL (Bitfield-Mask: 0x01)                          */
#define IPWM_POL_CH1POL_Pos               (1UL)                     /*!< CH1POL (Bit 1)                                        */
#define IPWM_POL_CH1POL_Msk               (0x2UL)                   /*!< CH1POL (Bitfield-Mask: 0x01)                          */
#define IPWM_POL_CH2POL_Pos               (2UL)                     /*!< CH2POL (Bit 2)                                        */
#define IPWM_POL_CH2POL_Msk               (0x4UL)                   /*!< CH2POL (Bitfield-Mask: 0x01)                          */
#define IPWM_POL_CH3POL_Pos               (3UL)                     /*!< CH3POL (Bit 3)                                        */
#define IPWM_POL_CH3POL_Msk               (0x8UL)                   /*!< CH3POL (Bitfield-Mask: 0x01)                          */
/* ========================================================  SYNCONF  ======================================================== */
#define IPWM_SYNCONF_CH0SYNCEN_Pos        (0UL)                     /*!< CH0SYNCEN (Bit 0)                                     */
#define IPWM_SYNCONF_CH0SYNCEN_Msk        (0x1UL)                   /*!< CH0SYNCEN (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNCONF_CH0SWRSTCNT_Pos      (4UL)                     /*!< CH0SWRSTCNT (Bit 4)                                   */
#define IPWM_SYNCONF_CH0SWRSTCNT_Msk      (0x10UL)                  /*!< CH0SWRSTCNT (Bitfield-Mask: 0x01)                     */
#define IPWM_SYNCONF_CH0SWWRBUF_Pos       (5UL)                     /*!< CH0SWWRBUF (Bit 5)                                    */
#define IPWM_SYNCONF_CH0SWWRBUF_Msk       (0x20UL)                  /*!< CH0SWWRBUF (Bitfield-Mask: 0x01)                      */
#define IPWM_SYNCONF_CH1SYNCEN_Pos        (8UL)                     /*!< CH1SYNCEN (Bit 8)                                     */
#define IPWM_SYNCONF_CH1SYNCEN_Msk        (0x100UL)                 /*!< CH1SYNCEN (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNCONF_CH1SWRSTCNT_Pos      (12UL)                    /*!< CH1SWRSTCNT (Bit 12)                                  */
#define IPWM_SYNCONF_CH1SWRSTCNT_Msk      (0x1000UL)                /*!< CH1SWRSTCNT (Bitfield-Mask: 0x01)                     */
#define IPWM_SYNCONF_CH1SWWRBUF_Pos       (13UL)                    /*!< CH1SWWRBUF (Bit 13)                                   */
#define IPWM_SYNCONF_CH1SWWRBUF_Msk       (0x2000UL)                /*!< CH1SWWRBUF (Bitfield-Mask: 0x01)                      */
#define IPWM_SYNCONF_CH2SYNCEN_Pos        (16UL)                    /*!< CH2SYNCEN (Bit 16)                                    */
#define IPWM_SYNCONF_CH2SYNCEN_Msk        (0x10000UL)               /*!< CH2SYNCEN (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNCONF_CH2SWRSTCNT_Pos      (20UL)                    /*!< CH2SWRSTCNT (Bit 20)                                  */
#define IPWM_SYNCONF_CH2SWRSTCNT_Msk      (0x100000UL)              /*!< CH2SWRSTCNT (Bitfield-Mask: 0x01)                     */
#define IPWM_SYNCONF_CH2SWWRBUF_Pos       (21UL)                    /*!< CH2SWWRBUF (Bit 21)                                   */
#define IPWM_SYNCONF_CH2SWWRBUF_Msk       (0x200000UL)              /*!< CH2SWWRBUF (Bitfield-Mask: 0x01)                      */
#define IPWM_SYNCONF_CH3SYNCEN_Pos        (24UL)                    /*!< CH3SYNCEN (Bit 24)                                    */
#define IPWM_SYNCONF_CH3SYNCEN_Msk        (0x1000000UL)             /*!< CH3SYNCEN (Bitfield-Mask: 0x01)                       */
#define IPWM_SYNCONF_CH3SWRSTCNT_Pos      (28UL)                    /*!< CH3SWRSTCNT (Bit 28)                                  */
#define IPWM_SYNCONF_CH3SWRSTCNT_Msk      (0x10000000UL)            /*!< CH3SWRSTCNT (Bitfield-Mask: 0x01)                     */
#define IPWM_SYNCONF_CH3SWWRBUF_Pos       (29UL)                    /*!< CH3SWWRBUF (Bit 29)                                   */
#define IPWM_SYNCONF_CH3SWWRBUF_Msk       (0x20000000UL)            /*!< CH3SWWRBUF (Bitfield-Mask: 0x01)                      */
/* =========================================================  CONF  ========================================================== */
#define IPWM_CONF_GTBEOUT_Pos             (0UL)                     /*!< GTBEOUT (Bit 0)                                       */
#define IPWM_CONF_GTBEOUT_Msk             (0x1UL)                   /*!< GTBEOUT (Bitfield-Mask: 0x01)                         */
#define IPWM_CONF_GTBEEN_Pos              (1UL)                     /*!< GTBEEN (Bit 1)                                        */
#define IPWM_CONF_GTBEEN_Msk              (0x2UL)                   /*!< GTBEEN (Bitfield-Mask: 0x01)                          */
/* =====================================================  CH0CVaDITHER  ====================================================== */
#define IPWM_CH0CVaDITHER_CVaDITHER_Pos   (0UL)                     /*!< CVaDITHER (Bit 0)                                     */
#define IPWM_CH0CVaDITHER_CVaDITHER_Msk   (0x1fUL)                  /*!< CVaDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH1CVaDITHER  ====================================================== */
#define IPWM_CH1CVaDITHER_CVaDITHER_Pos   (0UL)                     /*!< CVaDITHER (Bit 0)                                     */
#define IPWM_CH1CVaDITHER_CVaDITHER_Msk   (0x1fUL)                  /*!< CVaDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH2CVaDITHER  ====================================================== */
#define IPWM_CH2CVaDITHER_CVaDITHER_Pos   (0UL)                     /*!< CVaDITHER (Bit 0)                                     */
#define IPWM_CH2CVaDITHER_CVaDITHER_Msk   (0x1fUL)                  /*!< CVaDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH3CVaDITHER  ====================================================== */
#define IPWM_CH3CVaDITHER_CVaDITHER_Pos   (0UL)                     /*!< CVaDITHER (Bit 0)                                     */
#define IPWM_CH3CVaDITHER_CVaDITHER_Msk   (0x1fUL)                  /*!< CVaDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH0CVbDITHER  ====================================================== */
#define IPWM_CH0CVbDITHER_CVbDITHER_Pos   (0UL)                     /*!< CVbDITHER (Bit 0)                                     */
#define IPWM_CH0CVbDITHER_CVbDITHER_Msk   (0x1fUL)                  /*!< CVbDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH1CVbDITHER  ====================================================== */
#define IPWM_CH1CVbDITHER_CVbDITHER_Pos   (0UL)                     /*!< CVbDITHER (Bit 0)                                     */
#define IPWM_CH1CVbDITHER_CVbDITHER_Msk   (0x1fUL)                  /*!< CVbDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH2CVbDITHER  ====================================================== */
#define IPWM_CH2CVbDITHER_CVbDITHER_Pos   (0UL)                     /*!< CVbDITHER (Bit 0)                                     */
#define IPWM_CH2CVbDITHER_CVbDITHER_Msk   (0x1fUL)                  /*!< CVbDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH3CVbDITHER  ====================================================== */
#define IPWM_CH3CVbDITHER_CVbDITHER_Pos   (0UL)                     /*!< CVbDITHER (Bit 0)                                     */
#define IPWM_CH3CVbDITHER_CVbDITHER_Msk   (0x1fUL)                  /*!< CVbDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH0MODDITHER  ====================================================== */
#define IPWM_CH0MODDITHER_MODDITHER_Pos   (0UL)                     /*!< MODDITHER (Bit 0)                                     */
#define IPWM_CH0MODDITHER_MODDITHER_Msk   (0x1fUL)                  /*!< MODDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH1MODDITHER  ====================================================== */
#define IPWM_CH1MODDITHER_MODDITHER_Pos   (0UL)                     /*!< MODDITHER (Bit 0)                                     */
#define IPWM_CH1MODDITHER_MODDITHER_Msk   (0x1fUL)                  /*!< MODDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH2MODDITHER  ====================================================== */
#define IPWM_CH2MODDITHER_MODDITHER_Pos   (0UL)                     /*!< MODDITHER (Bit 0)                                     */
#define IPWM_CH2MODDITHER_MODDITHER_Msk   (0x1fUL)                  /*!< MODDITHER (Bitfield-Mask: 0x1f)                       */
/* =====================================================  CH3MODDITHER  ====================================================== */
#define IPWM_CH3MODDITHER_MODDITHER_Pos   (0UL)                     /*!< MODDITHER (Bit 0)                                     */
#define IPWM_CH3MODDITHER_MODDITHER_Msk   (0x1fUL)                  /*!< MODDITHER (Bitfield-Mask: 0x1f)                       */

/* =========================================================================================================================== */
/* ================                                           SPWM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SC  =========================================================== */
#define SPWM_SC_CNTEN_Pos                 (0UL)                     /*!< CNTEN (Bit 0)                                         */
#define SPWM_SC_CNTEN_Msk                 (0x1UL)                   /*!< CNTEN (Bitfield-Mask: 0x01)                           */
#define SPWM_SC_CPWMS_Pos                 (1UL)                     /*!< CPWMS (Bit 1)                                         */
#define SPWM_SC_CPWMS_Msk                 (0x2UL)                   /*!< CPWMS (Bitfield-Mask: 0x01)                           */
#define SPWM_SC_COIE_Pos                  (4UL)                     /*!< COIE (Bit 4)                                          */
#define SPWM_SC_COIE_Msk                  (0x10UL)                  /*!< COIE (Bitfield-Mask: 0x01)                            */
#define SPWM_SC_CUIE_Pos                  (5UL)                     /*!< CUIE (Bit 5)                                          */
#define SPWM_SC_CUIE_Msk                  (0x20UL)                  /*!< CUIE (Bitfield-Mask: 0x01)                            */
#define SPWM_SC_COFNUM_Pos                (8UL)                     /*!< COFNUM (Bit 8)                                        */
#define SPWM_SC_COFNUM_Msk                (0x1f00UL)                /*!< COFNUM (Bitfield-Mask: 0x1f)                          */
#define SPWM_SC_COF_Pos                   (14UL)                    /*!< COF (Bit 14)                                          */
#define SPWM_SC_COF_Msk                   (0x4000UL)                /*!< COF (Bitfield-Mask: 0x01)                             */
#define SPWM_SC_CUF_Pos                   (15UL)                    /*!< CUF (Bit 15)                                          */
#define SPWM_SC_CUF_Msk                   (0x8000UL)                /*!< CUF (Bitfield-Mask: 0x01)                             */
#define SPWM_SC_PSC_Pos                   (16UL)                    /*!< PSC (Bit 16)                                          */
#define SPWM_SC_PSC_Msk                   (0xff0000UL)              /*!< PSC (Bitfield-Mask: 0xff)                             */
/* ==========================================================  CNT  ========================================================== */
#define SPWM_CNT_COUNT_Pos                (0UL)                     /*!< COUNT (Bit 0)                                         */
#define SPWM_CNT_COUNT_Msk                (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  MOD  ========================================================== */
#define SPWM_MOD_MOD_Pos                  (0UL)                     /*!< MOD (Bit 0)                                           */
#define SPWM_MOD_MOD_Msk                  (0xffffUL)                /*!< MOD (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CNTIN  ========================================================= */
#define SPWM_CNTIN_CNTIN_Pos              (0UL)                     /*!< CNTIN (Bit 0)                                         */
#define SPWM_CNTIN_CNTIN_Msk              (0xffffUL)                /*!< CNTIN (Bitfield-Mask: 0xffff)                         */
/* =========================================================  C0SC  ========================================================== */
#define SPWM_C0SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C0SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C0SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C0SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C0SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C0SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C0SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C0SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C0SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C0SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C0SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C0SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C0SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C0SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C1SC  ========================================================== */
#define SPWM_C1SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C1SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C1SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C1SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C1SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C1SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C1SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C1SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C1SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C1SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C1SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C1SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C1SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C1SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C2SC  ========================================================== */
#define SPWM_C2SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C2SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C2SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C2SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C2SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C2SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C2SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C2SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C2SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C2SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C2SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C2SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C2SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C2SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C3SC  ========================================================== */
#define SPWM_C3SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C3SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C3SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C3SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C3SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C3SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C3SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C3SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C3SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C3SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C3SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C3SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C3SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C3SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C4SC  ========================================================== */
#define SPWM_C4SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C4SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C4SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C4SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C4SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C4SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C4SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C4SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C4SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C4SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C4SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C4SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C4SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C4SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C5SC  ========================================================== */
#define SPWM_C5SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C5SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C5SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C5SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C5SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C5SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C5SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C5SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C5SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C5SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C5SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C5SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C5SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C5SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C6SC  ========================================================== */
#define SPWM_C6SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C6SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C6SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C6SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C6SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C6SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C6SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C6SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C6SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C6SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C6SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C6SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C6SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C6SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* =========================================================  C7SC  ========================================================== */
#define SPWM_C7SC_ICRST_Pos               (0UL)                     /*!< ICRST (Bit 0)                                         */
#define SPWM_C7SC_ICRST_Msk               (0x1UL)                   /*!< ICRST (Bitfield-Mask: 0x01)                           */
#define SPWM_C7SC_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define SPWM_C7SC_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define SPWM_C7SC_ELS_Pos                 (4UL)                     /*!< ELS (Bit 4)                                           */
#define SPWM_C7SC_ELS_Msk                 (0x30UL)                  /*!< ELS (Bitfield-Mask: 0x03)                             */
#define SPWM_C7SC_MSEL_Pos                (6UL)                     /*!< MSEL (Bit 6)                                          */
#define SPWM_C7SC_MSEL_Msk                (0xc0UL)                  /*!< MSEL (Bitfield-Mask: 0x03)                            */
#define SPWM_C7SC_CHIE_Pos                (8UL)                     /*!< CHIE (Bit 8)                                          */
#define SPWM_C7SC_CHIE_Msk                (0x100UL)                 /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define SPWM_C7SC_CHF_Pos                 (9UL)                     /*!< CHF (Bit 9)                                           */
#define SPWM_C7SC_CHF_Msk                 (0x200UL)                 /*!< CHF (Bitfield-Mask: 0x01)                             */
#define SPWM_C7SC_CHFPSC_Pos              (12UL)                    /*!< CHFPSC (Bit 12)                                       */
#define SPWM_C7SC_CHFPSC_Msk              (0x3000UL)                /*!< CHFPSC (Bitfield-Mask: 0x03)                          */
/* ==========================================================  C0V  ========================================================== */
#define SPWM_C0V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C0V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C1V  ========================================================== */
#define SPWM_C1V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C1V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C2V  ========================================================== */
#define SPWM_C2V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C2V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C3V  ========================================================== */
#define SPWM_C3V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C3V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C4V  ========================================================== */
#define SPWM_C4V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C4V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C5V  ========================================================== */
#define SPWM_C5V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C5V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C6V  ========================================================== */
#define SPWM_C6V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C6V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  C7V  ========================================================== */
#define SPWM_C7V_VAL_Pos                  (0UL)                     /*!< VAL (Bit 0)                                           */
#define SPWM_C7V_VAL_Msk                  (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ========================================================  STATUS  ========================================================= */
#define SPWM_STATUS_CH0F_Pos              (0UL)                     /*!< CH0F (Bit 0)                                          */
#define SPWM_STATUS_CH0F_Msk              (0x1UL)                   /*!< CH0F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH1F_Pos              (1UL)                     /*!< CH1F (Bit 1)                                          */
#define SPWM_STATUS_CH1F_Msk              (0x2UL)                   /*!< CH1F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH2F_Pos              (2UL)                     /*!< CH2F (Bit 2)                                          */
#define SPWM_STATUS_CH2F_Msk              (0x4UL)                   /*!< CH2F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH3F_Pos              (3UL)                     /*!< CH3F (Bit 3)                                          */
#define SPWM_STATUS_CH3F_Msk              (0x8UL)                   /*!< CH3F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH4F_Pos              (4UL)                     /*!< CH4F (Bit 4)                                          */
#define SPWM_STATUS_CH4F_Msk              (0x10UL)                  /*!< CH4F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH5F_Pos              (5UL)                     /*!< CH5F (Bit 5)                                          */
#define SPWM_STATUS_CH5F_Msk              (0x20UL)                  /*!< CH5F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH6F_Pos              (6UL)                     /*!< CH6F (Bit 6)                                          */
#define SPWM_STATUS_CH6F_Msk              (0x40UL)                  /*!< CH6F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH7F_Pos              (7UL)                     /*!< CH7F (Bit 7)                                          */
#define SPWM_STATUS_CH7F_Msk              (0x80UL)                  /*!< CH7F (Bitfield-Mask: 0x01)                            */
#define SPWM_STATUS_CH0LVL_Pos            (8UL)                     /*!< CH0LVL (Bit 8)                                        */
#define SPWM_STATUS_CH0LVL_Msk            (0x100UL)                 /*!< CH0LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH1LVL_Pos            (9UL)                     /*!< CH1LVL (Bit 9)                                        */
#define SPWM_STATUS_CH1LVL_Msk            (0x200UL)                 /*!< CH1LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH2LVL_Pos            (10UL)                    /*!< CH2LVL (Bit 10)                                       */
#define SPWM_STATUS_CH2LVL_Msk            (0x400UL)                 /*!< CH2LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH3LVL_Pos            (11UL)                    /*!< CH3LVL (Bit 11)                                       */
#define SPWM_STATUS_CH3LVL_Msk            (0x800UL)                 /*!< CH3LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH4LVL_Pos            (12UL)                    /*!< CH4LVL (Bit 12)                                       */
#define SPWM_STATUS_CH4LVL_Msk            (0x1000UL)                /*!< CH4LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH5LVL_Pos            (13UL)                    /*!< CH5LVL (Bit 13)                                       */
#define SPWM_STATUS_CH5LVL_Msk            (0x2000UL)                /*!< CH5LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH6LVL_Pos            (14UL)                    /*!< CH6LVL (Bit 14)                                       */
#define SPWM_STATUS_CH6LVL_Msk            (0x4000UL)                /*!< CH6LVL (Bitfield-Mask: 0x01)                          */
#define SPWM_STATUS_CH7LVL_Pos            (15UL)                    /*!< CH7LVL (Bit 15)                                       */
#define SPWM_STATUS_CH7LVL_Msk            (0x8000UL)                /*!< CH7LVL (Bitfield-Mask: 0x01)                          */
/* =========================================================  MODE  ========================================================== */
#define SPWM_MODE_PWMSYNCEN_Pos           (0UL)                     /*!< PWMSYNCEN (Bit 0)                                     */
#define SPWM_MODE_PWMSYNCEN_Msk           (0x1UL)                   /*!< PWMSYNCEN (Bitfield-Mask: 0x01)                       */
#define SPWM_MODE_INIT_Pos                (1UL)                     /*!< INIT (Bit 1)                                          */
#define SPWM_MODE_INIT_Msk                (0x2UL)                   /*!< INIT (Bitfield-Mask: 0x01)                            */
#define SPWM_MODE_WPDIS_Pos               (2UL)                     /*!< WPDIS (Bit 2)                                         */
#define SPWM_MODE_WPDIS_Msk               (0x4UL)                   /*!< WPDIS (Bitfield-Mask: 0x01)                           */
#define SPWM_MODE_BUFFRD_Pos              (4UL)                     /*!< BUFFRD (Bit 4)                                        */
#define SPWM_MODE_BUFFRD_Msk              (0x10UL)                  /*!< BUFFRD (Bitfield-Mask: 0x01)                          */
#define SPWM_MODE_FAULTM_Pos              (5UL)                     /*!< FAULTM (Bit 5)                                        */
#define SPWM_MODE_FAULTM_Msk              (0x20UL)                  /*!< FAULTM (Bitfield-Mask: 0x01)                          */
#define SPWM_MODE_FAULTEN_Pos             (6UL)                     /*!< FAULTEN (Bit 6)                                       */
#define SPWM_MODE_FAULTEN_Msk             (0x40UL)                  /*!< FAULTEN (Bitfield-Mask: 0x01)                         */
#define SPWM_MODE_FAULTIE_Pos             (7UL)                     /*!< FAULTIE (Bit 7)                                       */
#define SPWM_MODE_FAULTIE_Msk             (0x80UL)                  /*!< FAULTIE (Bitfield-Mask: 0x01)                         */
#define SPWM_MODE_HALL_Pos                (8UL)                     /*!< HALL (Bit 8)                                          */
#define SPWM_MODE_HALL_Msk                (0x100UL)                 /*!< HALL (Bitfield-Mask: 0x01)                            */
/* =========================================================  SYNC  ========================================================== */
#define SPWM_SYNC_CNTMIN_Pos              (0UL)                     /*!< CNTMIN (Bit 0)                                        */
#define SPWM_SYNC_CNTMIN_Msk              (0x1UL)                   /*!< CNTMIN (Bitfield-Mask: 0x01)                          */
#define SPWM_SYNC_CNTMAX_Pos              (1UL)                     /*!< CNTMAX (Bit 1)                                        */
#define SPWM_SYNC_CNTMAX_Msk              (0x2UL)                   /*!< CNTMAX (Bitfield-Mask: 0x01)                          */
#define SPWM_SYNC_SYNCHOM_Pos             (3UL)                     /*!< SYNCHOM (Bit 3)                                       */
#define SPWM_SYNC_SYNCHOM_Msk             (0x8UL)                   /*!< SYNCHOM (Bitfield-Mask: 0x01)                         */
#define SPWM_SYNC_TRIG0_Pos               (4UL)                     /*!< TRIG0 (Bit 4)                                         */
#define SPWM_SYNC_TRIG0_Msk               (0x10UL)                  /*!< TRIG0 (Bitfield-Mask: 0x01)                           */
#define SPWM_SYNC_TRIG1_Pos               (5UL)                     /*!< TRIG1 (Bit 5)                                         */
#define SPWM_SYNC_TRIG1_Msk               (0x20UL)                  /*!< TRIG1 (Bitfield-Mask: 0x01)                           */
#define SPWM_SYNC_SWSYNC_Pos              (7UL)                     /*!< SWSYNC (Bit 7)                                        */
#define SPWM_SYNC_SWSYNC_Msk              (0x80UL)                  /*!< SWSYNC (Bitfield-Mask: 0x01)                          */
/* ========================================================  OUTINIT  ======================================================== */
#define SPWM_OUTINIT_CH0OI_Pos            (0UL)                     /*!< CH0OI (Bit 0)                                         */
#define SPWM_OUTINIT_CH0OI_Msk            (0x1UL)                   /*!< CH0OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH1OI_Pos            (1UL)                     /*!< CH1OI (Bit 1)                                         */
#define SPWM_OUTINIT_CH1OI_Msk            (0x2UL)                   /*!< CH1OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH2OI_Pos            (2UL)                     /*!< CH2OI (Bit 2)                                         */
#define SPWM_OUTINIT_CH2OI_Msk            (0x4UL)                   /*!< CH2OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH3OI_Pos            (3UL)                     /*!< CH3OI (Bit 3)                                         */
#define SPWM_OUTINIT_CH3OI_Msk            (0x8UL)                   /*!< CH3OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH4OI_Pos            (4UL)                     /*!< CH4OI (Bit 4)                                         */
#define SPWM_OUTINIT_CH4OI_Msk            (0x10UL)                  /*!< CH4OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH5OI_Pos            (5UL)                     /*!< CH5OI (Bit 5)                                         */
#define SPWM_OUTINIT_CH5OI_Msk            (0x20UL)                  /*!< CH5OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH6OI_Pos            (6UL)                     /*!< CH6OI (Bit 6)                                         */
#define SPWM_OUTINIT_CH6OI_Msk            (0x40UL)                  /*!< CH6OI (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTINIT_CH7OI_Pos            (7UL)                     /*!< CH7OI (Bit 7)                                         */
#define SPWM_OUTINIT_CH7OI_Msk            (0x80UL)                  /*!< CH7OI (Bitfield-Mask: 0x01)                           */
/* ========================================================  OUTMASK  ======================================================== */
#define SPWM_OUTMASK_CH0OM_Pos            (0UL)                     /*!< CH0OM (Bit 0)                                         */
#define SPWM_OUTMASK_CH0OM_Msk            (0x1UL)                   /*!< CH0OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH1OM_Pos            (1UL)                     /*!< CH1OM (Bit 1)                                         */
#define SPWM_OUTMASK_CH1OM_Msk            (0x2UL)                   /*!< CH1OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH2OM_Pos            (2UL)                     /*!< CH2OM (Bit 2)                                         */
#define SPWM_OUTMASK_CH2OM_Msk            (0x4UL)                   /*!< CH2OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH3OM_Pos            (3UL)                     /*!< CH3OM (Bit 3)                                         */
#define SPWM_OUTMASK_CH3OM_Msk            (0x8UL)                   /*!< CH3OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH4OM_Pos            (4UL)                     /*!< CH4OM (Bit 4)                                         */
#define SPWM_OUTMASK_CH4OM_Msk            (0x10UL)                  /*!< CH4OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH5OM_Pos            (5UL)                     /*!< CH5OM (Bit 5)                                         */
#define SPWM_OUTMASK_CH5OM_Msk            (0x20UL)                  /*!< CH5OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH6OM_Pos            (6UL)                     /*!< CH6OM (Bit 6)                                         */
#define SPWM_OUTMASK_CH6OM_Msk            (0x40UL)                  /*!< CH6OM (Bitfield-Mask: 0x01)                           */
#define SPWM_OUTMASK_CH7OM_Pos            (7UL)                     /*!< CH7OM (Bit 7)                                         */
#define SPWM_OUTMASK_CH7OM_Msk            (0x80UL)                  /*!< CH7OM (Bitfield-Mask: 0x01)                           */
/* ========================================================  COMBINE  ======================================================== */
#define SPWM_COMBINE_COMBINE0_Pos         (0UL)                     /*!< COMBINE0 (Bit 0)                                      */
#define SPWM_COMBINE_COMBINE0_Msk         (0x1UL)                   /*!< COMBINE0 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_COMP0_Pos            (1UL)                     /*!< COMP0 (Bit 1)                                         */
#define SPWM_COMBINE_COMP0_Msk            (0x2UL)                   /*!< COMP0 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_DECAPEN0_Pos         (2UL)                     /*!< DECAPEN0 (Bit 2)                                      */
#define SPWM_COMBINE_DECAPEN0_Msk         (0x4UL)                   /*!< DECAPEN0 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_DECAP0_Pos           (3UL)                     /*!< DECAP0 (Bit 3)                                        */
#define SPWM_COMBINE_DECAP0_Msk           (0x8UL)                   /*!< DECAP0 (Bitfield-Mask: 0x01)                          */
#define SPWM_COMBINE_DTEN0_Pos            (4UL)                     /*!< DTEN0 (Bit 4)                                         */
#define SPWM_COMBINE_DTEN0_Msk            (0x10UL)                  /*!< DTEN0 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_SYNCEN0_Pos          (5UL)                     /*!< SYNCEN0 (Bit 5)                                       */
#define SPWM_COMBINE_SYNCEN0_Msk          (0x20UL)                  /*!< SYNCEN0 (Bitfield-Mask: 0x01)                         */
#define SPWM_COMBINE_FAULTEN0_Pos         (6UL)                     /*!< FAULTEN0 (Bit 6)                                      */
#define SPWM_COMBINE_FAULTEN0_Msk         (0x40UL)                  /*!< FAULTEN0 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_SYMM0_Pos            (7UL)                     /*!< SYMM0 (Bit 7)                                         */
#define SPWM_COMBINE_SYMM0_Msk            (0x80UL)                  /*!< SYMM0 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_COMBINE1_Pos         (8UL)                     /*!< COMBINE1 (Bit 8)                                      */
#define SPWM_COMBINE_COMBINE1_Msk         (0x100UL)                 /*!< COMBINE1 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_COMP1_Pos            (9UL)                     /*!< COMP1 (Bit 9)                                         */
#define SPWM_COMBINE_COMP1_Msk            (0x200UL)                 /*!< COMP1 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_DECAPEN1_Pos         (10UL)                    /*!< DECAPEN1 (Bit 10)                                     */
#define SPWM_COMBINE_DECAPEN1_Msk         (0x400UL)                 /*!< DECAPEN1 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_DECAP1_Pos           (11UL)                    /*!< DECAP1 (Bit 11)                                       */
#define SPWM_COMBINE_DECAP1_Msk           (0x800UL)                 /*!< DECAP1 (Bitfield-Mask: 0x01)                          */
#define SPWM_COMBINE_DTEN1_Pos            (12UL)                    /*!< DTEN1 (Bit 12)                                        */
#define SPWM_COMBINE_DTEN1_Msk            (0x1000UL)                /*!< DTEN1 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_SYNCEN1_Pos          (13UL)                    /*!< SYNCEN1 (Bit 13)                                      */
#define SPWM_COMBINE_SYNCEN1_Msk          (0x2000UL)                /*!< SYNCEN1 (Bitfield-Mask: 0x01)                         */
#define SPWM_COMBINE_FAULTEN1_Pos         (14UL)                    /*!< FAULTEN1 (Bit 14)                                     */
#define SPWM_COMBINE_FAULTEN1_Msk         (0x4000UL)                /*!< FAULTEN1 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_SYMM1_Pos            (15UL)                    /*!< SYMM1 (Bit 15)                                        */
#define SPWM_COMBINE_SYMM1_Msk            (0x8000UL)                /*!< SYMM1 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_COMBINE2_Pos         (16UL)                    /*!< COMBINE2 (Bit 16)                                     */
#define SPWM_COMBINE_COMBINE2_Msk         (0x10000UL)               /*!< COMBINE2 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_COMP2_Pos            (17UL)                    /*!< COMP2 (Bit 17)                                        */
#define SPWM_COMBINE_COMP2_Msk            (0x20000UL)               /*!< COMP2 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_DECAPEN2_Pos         (18UL)                    /*!< DECAPEN2 (Bit 18)                                     */
#define SPWM_COMBINE_DECAPEN2_Msk         (0x40000UL)               /*!< DECAPEN2 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_DECAP2_Pos           (19UL)                    /*!< DECAP2 (Bit 19)                                       */
#define SPWM_COMBINE_DECAP2_Msk           (0x80000UL)               /*!< DECAP2 (Bitfield-Mask: 0x01)                          */
#define SPWM_COMBINE_DTEN2_Pos            (20UL)                    /*!< DTEN2 (Bit 20)                                        */
#define SPWM_COMBINE_DTEN2_Msk            (0x100000UL)              /*!< DTEN2 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_SYNCEN2_Pos          (21UL)                    /*!< SYNCEN2 (Bit 21)                                      */
#define SPWM_COMBINE_SYNCEN2_Msk          (0x200000UL)              /*!< SYNCEN2 (Bitfield-Mask: 0x01)                         */
#define SPWM_COMBINE_FAULTEN2_Pos         (22UL)                    /*!< FAULTEN2 (Bit 22)                                     */
#define SPWM_COMBINE_FAULTEN2_Msk         (0x400000UL)              /*!< FAULTEN2 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_SYMM2_Pos            (23UL)                    /*!< SYMM2 (Bit 23)                                        */
#define SPWM_COMBINE_SYMM2_Msk            (0x800000UL)              /*!< SYMM2 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_COMBINE3_Pos         (24UL)                    /*!< COMBINE3 (Bit 24)                                     */
#define SPWM_COMBINE_COMBINE3_Msk         (0x1000000UL)             /*!< COMBINE3 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_COMP3_Pos            (25UL)                    /*!< COMP3 (Bit 25)                                        */
#define SPWM_COMBINE_COMP3_Msk            (0x2000000UL)             /*!< COMP3 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_DECAPEN3_Pos         (26UL)                    /*!< DECAPEN3 (Bit 26)                                     */
#define SPWM_COMBINE_DECAPEN3_Msk         (0x4000000UL)             /*!< DECAPEN3 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_DECAP3_Pos           (27UL)                    /*!< DECAP3 (Bit 27)                                       */
#define SPWM_COMBINE_DECAP3_Msk           (0x8000000UL)             /*!< DECAP3 (Bitfield-Mask: 0x01)                          */
#define SPWM_COMBINE_DTEN3_Pos            (28UL)                    /*!< DTEN3 (Bit 28)                                        */
#define SPWM_COMBINE_DTEN3_Msk            (0x10000000UL)            /*!< DTEN3 (Bitfield-Mask: 0x01)                           */
#define SPWM_COMBINE_SYNCEN3_Pos          (29UL)                    /*!< SYNCEN3 (Bit 29)                                      */
#define SPWM_COMBINE_SYNCEN3_Msk          (0x20000000UL)            /*!< SYNCEN3 (Bitfield-Mask: 0x01)                         */
#define SPWM_COMBINE_FAULTEN3_Pos         (30UL)                    /*!< FAULTEN3 (Bit 30)                                     */
#define SPWM_COMBINE_FAULTEN3_Msk         (0x40000000UL)            /*!< FAULTEN3 (Bitfield-Mask: 0x01)                        */
#define SPWM_COMBINE_SYMM3_Pos            (31UL)                    /*!< SYMM3 (Bit 31)                                        */
#define SPWM_COMBINE_SYMM3_Msk            (0x80000000UL)            /*!< SYMM3 (Bitfield-Mask: 0x01)                           */
/* ========================================================  EXTTRIG  ======================================================== */
#define SPWM_EXTTRIG_CH0MATCHTRIG_Pos     (0UL)                     /*!< CH0MATCHTRIG (Bit 0)                                  */
#define SPWM_EXTTRIG_CH0MATCHTRIG_Msk     (0x1UL)                   /*!< CH0MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH1MATCHTRIG_Pos     (1UL)                     /*!< CH1MATCHTRIG (Bit 1)                                  */
#define SPWM_EXTTRIG_CH1MATCHTRIG_Msk     (0x2UL)                   /*!< CH1MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH2MATCHTRIG_Pos     (2UL)                     /*!< CH2MATCHTRIG (Bit 2)                                  */
#define SPWM_EXTTRIG_CH2MATCHTRIG_Msk     (0x4UL)                   /*!< CH2MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH3MATCHTRIG_Pos     (3UL)                     /*!< CH3MATCHTRIG (Bit 3)                                  */
#define SPWM_EXTTRIG_CH3MATCHTRIG_Msk     (0x8UL)                   /*!< CH3MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH4MATCHTRIG_Pos     (4UL)                     /*!< CH4MATCHTRIG (Bit 4)                                  */
#define SPWM_EXTTRIG_CH4MATCHTRIG_Msk     (0x10UL)                  /*!< CH4MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH5MATCHTRIG_Pos     (5UL)                     /*!< CH5MATCHTRIG (Bit 5)                                  */
#define SPWM_EXTTRIG_CH5MATCHTRIG_Msk     (0x20UL)                  /*!< CH5MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH6MATCHTRIG_Pos     (6UL)                     /*!< CH6MATCHTRIG (Bit 6)                                  */
#define SPWM_EXTTRIG_CH6MATCHTRIG_Msk     (0x40UL)                  /*!< CH6MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_CH7MATCHTRIG_Pos     (7UL)                     /*!< CH7MATCHTRIG (Bit 7)                                  */
#define SPWM_EXTTRIG_CH7MATCHTRIG_Msk     (0x80UL)                  /*!< CH7MATCHTRIG (Bitfield-Mask: 0x01)                    */
#define SPWM_EXTTRIG_MINTRIG_Pos          (8UL)                     /*!< MINTRIG (Bit 8)                                       */
#define SPWM_EXTTRIG_MINTRIG_Msk          (0x100UL)                 /*!< MINTRIG (Bitfield-Mask: 0x01)                         */
#define SPWM_EXTTRIG_MAXTRIG_Pos          (9UL)                     /*!< MAXTRIG (Bit 9)                                       */
#define SPWM_EXTTRIG_MAXTRIG_Msk          (0x200UL)                 /*!< MAXTRIG (Bitfield-Mask: 0x01)                         */
#define SPWM_EXTTRIG_TRIGF_Pos            (10UL)                    /*!< TRIGF (Bit 10)                                        */
#define SPWM_EXTTRIG_TRIGF_Msk            (0x400UL)                 /*!< TRIGF (Bitfield-Mask: 0x01)                           */
#define SPWM_EXTTRIG_TRIGPSC_Pos          (12UL)                    /*!< TRIGPSC (Bit 12)                                      */
#define SPWM_EXTTRIG_TRIGPSC_Msk          (0x7000UL)                /*!< TRIGPSC (Bitfield-Mask: 0x07)                         */
/* ==========================================================  POL  ========================================================== */
#define SPWM_POL_CH0POL_Pos               (0UL)                     /*!< CH0POL (Bit 0)                                        */
#define SPWM_POL_CH0POL_Msk               (0x1UL)                   /*!< CH0POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH1POL_Pos               (1UL)                     /*!< CH1POL (Bit 1)                                        */
#define SPWM_POL_CH1POL_Msk               (0x2UL)                   /*!< CH1POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH2POL_Pos               (2UL)                     /*!< CH2POL (Bit 2)                                        */
#define SPWM_POL_CH2POL_Msk               (0x4UL)                   /*!< CH2POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH3POL_Pos               (3UL)                     /*!< CH3POL (Bit 3)                                        */
#define SPWM_POL_CH3POL_Msk               (0x8UL)                   /*!< CH3POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH4POL_Pos               (4UL)                     /*!< CH4POL (Bit 4)                                        */
#define SPWM_POL_CH4POL_Msk               (0x10UL)                  /*!< CH4POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH5POL_Pos               (5UL)                     /*!< CH5POL (Bit 5)                                        */
#define SPWM_POL_CH5POL_Msk               (0x20UL)                  /*!< CH5POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH6POL_Pos               (6UL)                     /*!< CH6POL (Bit 6)                                        */
#define SPWM_POL_CH6POL_Msk               (0x40UL)                  /*!< CH6POL (Bitfield-Mask: 0x01)                          */
#define SPWM_POL_CH7POL_Pos               (7UL)                     /*!< CH7POL (Bit 7)                                        */
#define SPWM_POL_CH7POL_Msk               (0x80UL)                  /*!< CH7POL (Bitfield-Mask: 0x01)                          */
/* ==========================================================  FMS  ========================================================== */
#define SPWM_FMS_FAULTF0_Pos              (0UL)                     /*!< FAULTF0 (Bit 0)                                       */
#define SPWM_FMS_FAULTF0_Msk              (0x1UL)                   /*!< FAULTF0 (Bitfield-Mask: 0x01)                         */
#define SPWM_FMS_FAULTF1_Pos              (1UL)                     /*!< FAULTF1 (Bit 1)                                       */
#define SPWM_FMS_FAULTF1_Msk              (0x2UL)                   /*!< FAULTF1 (Bitfield-Mask: 0x01)                         */
#define SPWM_FMS_FAULTF2_Pos              (2UL)                     /*!< FAULTF2 (Bit 2)                                       */
#define SPWM_FMS_FAULTF2_Msk              (0x4UL)                   /*!< FAULTF2 (Bitfield-Mask: 0x01)                         */
#define SPWM_FMS_FAULTF3_Pos              (3UL)                     /*!< FAULTF3 (Bit 3)                                       */
#define SPWM_FMS_FAULTF3_Msk              (0x8UL)                   /*!< FAULTF3 (Bitfield-Mask: 0x01)                         */
#define SPWM_FMS_FAULTIN_Pos              (5UL)                     /*!< FAULTIN (Bit 5)                                       */
#define SPWM_FMS_FAULTIN_Msk              (0x20UL)                  /*!< FAULTIN (Bitfield-Mask: 0x01)                         */
#define SPWM_FMS_WPEN_Pos                 (6UL)                     /*!< WPEN (Bit 6)                                          */
#define SPWM_FMS_WPEN_Msk                 (0x40UL)                  /*!< WPEN (Bitfield-Mask: 0x01)                            */
#define SPWM_FMS_FAULTF_Pos               (7UL)                     /*!< FAULTF (Bit 7)                                        */
#define SPWM_FMS_FAULTF_Msk               (0x80UL)                  /*!< FAULTF (Bitfield-Mask: 0x01)                          */
/* ========================================================  FILTER  ========================================================= */
#define SPWM_FILTER_CH0FVAL_Pos           (0UL)                     /*!< CH0FVAL (Bit 0)                                       */
#define SPWM_FILTER_CH0FVAL_Msk           (0xfUL)                   /*!< CH0FVAL (Bitfield-Mask: 0x0f)                         */
#define SPWM_FILTER_CH1FVAL_Pos           (4UL)                     /*!< CH1FVAL (Bit 4)                                       */
#define SPWM_FILTER_CH1FVAL_Msk           (0xf0UL)                  /*!< CH1FVAL (Bitfield-Mask: 0x0f)                         */
#define SPWM_FILTER_CH2FVAL_Pos           (8UL)                     /*!< CH2FVAL (Bit 8)                                       */
#define SPWM_FILTER_CH2FVAL_Msk           (0xf00UL)                 /*!< CH2FVAL (Bitfield-Mask: 0x0f)                         */
#define SPWM_FILTER_CH3FVAL_Pos           (12UL)                    /*!< CH3FVAL (Bit 12)                                      */
#define SPWM_FILTER_CH3FVAL_Msk           (0xf000UL)                /*!< CH3FVAL (Bitfield-Mask: 0x0f)                         */
#define SPWM_FILTER_FILTPSC_Pos           (16UL)                    /*!< FILTPSC (Bit 16)                                      */
#define SPWM_FILTER_FILTPSC_Msk           (0xf0000UL)               /*!< FILTPSC (Bitfield-Mask: 0x0f)                         */
/* ========================================================  FLTCTRL  ======================================================== */
#define SPWM_FLTCTRL_FAULT0EN_Pos         (0UL)                     /*!< FAULT0EN (Bit 0)                                      */
#define SPWM_FLTCTRL_FAULT0EN_Msk         (0x1UL)                   /*!< FAULT0EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FAULT1EN_Pos         (1UL)                     /*!< FAULT1EN (Bit 1)                                      */
#define SPWM_FLTCTRL_FAULT1EN_Msk         (0x2UL)                   /*!< FAULT1EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FAULT2EN_Pos         (2UL)                     /*!< FAULT2EN (Bit 2)                                      */
#define SPWM_FLTCTRL_FAULT2EN_Msk         (0x4UL)                   /*!< FAULT2EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FAULT3EN_Pos         (3UL)                     /*!< FAULT3EN (Bit 3)                                      */
#define SPWM_FLTCTRL_FAULT3EN_Msk         (0x8UL)                   /*!< FAULT3EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FFLTR0EN_Pos         (4UL)                     /*!< FFLTR0EN (Bit 4)                                      */
#define SPWM_FLTCTRL_FFLTR0EN_Msk         (0x10UL)                  /*!< FFLTR0EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FFLTR1EN_Pos         (5UL)                     /*!< FFLTR1EN (Bit 5)                                      */
#define SPWM_FLTCTRL_FFLTR1EN_Msk         (0x20UL)                  /*!< FFLTR1EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FFLTR2EN_Pos         (6UL)                     /*!< FFLTR2EN (Bit 6)                                      */
#define SPWM_FLTCTRL_FFLTR2EN_Msk         (0x40UL)                  /*!< FFLTR2EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FFLTR3EN_Pos         (7UL)                     /*!< FFLTR3EN (Bit 7)                                      */
#define SPWM_FLTCTRL_FFLTR3EN_Msk         (0x80UL)                  /*!< FFLTR3EN (Bitfield-Mask: 0x01)                        */
#define SPWM_FLTCTRL_FFVAL_Pos            (8UL)                     /*!< FFVAL (Bit 8)                                         */
#define SPWM_FLTCTRL_FFVAL_Msk            (0xf00UL)                 /*!< FFVAL (Bitfield-Mask: 0x0f)                           */
#define SPWM_FLTCTRL_HIZ_Pos              (12UL)                    /*!< HIZ (Bit 12)                                          */
#define SPWM_FLTCTRL_HIZ_Msk              (0x1000UL)                /*!< HIZ (Bitfield-Mask: 0x01)                             */
/* =========================================================  CONF  ========================================================== */
#define SPWM_CONF_GTBEOUT_Pos             (0UL)                     /*!< GTBEOUT (Bit 0)                                       */
#define SPWM_CONF_GTBEOUT_Msk             (0x1UL)                   /*!< GTBEOUT (Bitfield-Mask: 0x01)                         */
#define SPWM_CONF_GTBEEN_Pos              (1UL)                     /*!< GTBEEN (Bit 1)                                        */
#define SPWM_CONF_GTBEEN_Msk              (0x2UL)                   /*!< GTBEEN (Bitfield-Mask: 0x01)                          */
/* ========================================================  FLTPOL  ========================================================= */
#define SPWM_FLTPOL_FLT0POL_Pos           (0UL)                     /*!< FLT0POL (Bit 0)                                       */
#define SPWM_FLTPOL_FLT0POL_Msk           (0x1UL)                   /*!< FLT0POL (Bitfield-Mask: 0x01)                         */
#define SPWM_FLTPOL_FLT1POL_Pos           (1UL)                     /*!< FLT1POL (Bit 1)                                       */
#define SPWM_FLTPOL_FLT1POL_Msk           (0x2UL)                   /*!< FLT1POL (Bitfield-Mask: 0x01)                         */
#define SPWM_FLTPOL_FLT2POL_Pos           (2UL)                     /*!< FLT2POL (Bit 2)                                       */
#define SPWM_FLTPOL_FLT2POL_Msk           (0x4UL)                   /*!< FLT2POL (Bitfield-Mask: 0x01)                         */
#define SPWM_FLTPOL_FLT3POL_Pos           (3UL)                     /*!< FLT3POL (Bit 3)                                       */
#define SPWM_FLTPOL_FLT3POL_Msk           (0x8UL)                   /*!< FLT3POL (Bitfield-Mask: 0x01)                         */
/* ========================================================  SYNCONF  ======================================================== */
#define SPWM_SYNCONF_HWTRIGMODE_Pos       (0UL)                     /*!< HWTRIGMODE (Bit 0)                                    */
#define SPWM_SYNCONF_HWTRIGMODE_Msk       (0x1UL)                   /*!< HWTRIGMODE (Bitfield-Mask: 0x01)                      */
#define SPWM_SYNCONF_INVC_Pos             (4UL)                     /*!< INVC (Bit 4)                                          */
#define SPWM_SYNCONF_INVC_Msk             (0x10UL)                  /*!< INVC (Bitfield-Mask: 0x01)                            */
#define SPWM_SYNCONF_SWOC_Pos             (5UL)                     /*!< SWOC (Bit 5)                                          */
#define SPWM_SYNCONF_SWOC_Msk             (0x20UL)                  /*!< SWOC (Bitfield-Mask: 0x01)                            */
#define SPWM_SYNCONF_SWRSTCNT_Pos         (8UL)                     /*!< SWRSTCNT (Bit 8)                                      */
#define SPWM_SYNCONF_SWRSTCNT_Msk         (0x100UL)                 /*!< SWRSTCNT (Bitfield-Mask: 0x01)                        */
#define SPWM_SYNCONF_SWWRBUF_Pos          (9UL)                     /*!< SWWRBUF (Bit 9)                                       */
#define SPWM_SYNCONF_SWWRBUF_Msk          (0x200UL)                 /*!< SWWRBUF (Bitfield-Mask: 0x01)                         */
#define SPWM_SYNCONF_SWOM_Pos             (10UL)                    /*!< SWOM (Bit 10)                                         */
#define SPWM_SYNCONF_SWOM_Msk             (0x400UL)                 /*!< SWOM (Bitfield-Mask: 0x01)                            */
#define SPWM_SYNCONF_SWINVC_Pos           (11UL)                    /*!< SWINVC (Bit 11)                                       */
#define SPWM_SYNCONF_SWINVC_Msk           (0x800UL)                 /*!< SWINVC (Bitfield-Mask: 0x01)                          */
#define SPWM_SYNCONF_SWSOC_Pos            (12UL)                    /*!< SWSOC (Bit 12)                                        */
#define SPWM_SYNCONF_SWSOC_Msk            (0x1000UL)                /*!< SWSOC (Bitfield-Mask: 0x01)                           */
#define SPWM_SYNCONF_HWRSTCNT_Pos         (16UL)                    /*!< HWRSTCNT (Bit 16)                                     */
#define SPWM_SYNCONF_HWRSTCNT_Msk         (0x10000UL)               /*!< HWRSTCNT (Bitfield-Mask: 0x01)                        */
#define SPWM_SYNCONF_HWWRBUF_Pos          (17UL)                    /*!< HWWRBUF (Bit 17)                                      */
#define SPWM_SYNCONF_HWWRBUF_Msk          (0x20000UL)               /*!< HWWRBUF (Bitfield-Mask: 0x01)                         */
#define SPWM_SYNCONF_HWOM_Pos             (18UL)                    /*!< HWOM (Bit 18)                                         */
#define SPWM_SYNCONF_HWOM_Msk             (0x40000UL)               /*!< HWOM (Bitfield-Mask: 0x01)                            */
#define SPWM_SYNCONF_HWINVC_Pos           (19UL)                    /*!< HWINVC (Bit 19)                                       */
#define SPWM_SYNCONF_HWINVC_Msk           (0x80000UL)               /*!< HWINVC (Bitfield-Mask: 0x01)                          */
#define SPWM_SYNCONF_HWSOC_Pos            (20UL)                    /*!< HWSOC (Bit 20)                                        */
#define SPWM_SYNCONF_HWSOC_Msk            (0x100000UL)              /*!< HWSOC (Bitfield-Mask: 0x01)                           */
/* ========================================================  INVCTRL  ======================================================== */
#define SPWM_INVCTRL_INV0EN_Pos           (0UL)                     /*!< INV0EN (Bit 0)                                        */
#define SPWM_INVCTRL_INV0EN_Msk           (0x1UL)                   /*!< INV0EN (Bitfield-Mask: 0x01)                          */
#define SPWM_INVCTRL_INV1EN_Pos           (1UL)                     /*!< INV1EN (Bit 1)                                        */
#define SPWM_INVCTRL_INV1EN_Msk           (0x2UL)                   /*!< INV1EN (Bitfield-Mask: 0x01)                          */
#define SPWM_INVCTRL_INV2EN_Pos           (2UL)                     /*!< INV2EN (Bit 2)                                        */
#define SPWM_INVCTRL_INV2EN_Msk           (0x4UL)                   /*!< INV2EN (Bitfield-Mask: 0x01)                          */
#define SPWM_INVCTRL_INV3EN_Pos           (3UL)                     /*!< INV3EN (Bit 3)                                        */
#define SPWM_INVCTRL_INV3EN_Msk           (0x8UL)                   /*!< INV3EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  SWOCTRL  ======================================================== */
#define SPWM_SWOCTRL_CH0OC_Pos            (0UL)                     /*!< CH0OC (Bit 0)                                         */
#define SPWM_SWOCTRL_CH0OC_Msk            (0x1UL)                   /*!< CH0OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH1OC_Pos            (1UL)                     /*!< CH1OC (Bit 1)                                         */
#define SPWM_SWOCTRL_CH1OC_Msk            (0x2UL)                   /*!< CH1OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH2OC_Pos            (2UL)                     /*!< CH2OC (Bit 2)                                         */
#define SPWM_SWOCTRL_CH2OC_Msk            (0x4UL)                   /*!< CH2OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH3OC_Pos            (3UL)                     /*!< CH3OC (Bit 3)                                         */
#define SPWM_SWOCTRL_CH3OC_Msk            (0x8UL)                   /*!< CH3OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH4OC_Pos            (4UL)                     /*!< CH4OC (Bit 4)                                         */
#define SPWM_SWOCTRL_CH4OC_Msk            (0x10UL)                  /*!< CH4OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH5OC_Pos            (5UL)                     /*!< CH5OC (Bit 5)                                         */
#define SPWM_SWOCTRL_CH5OC_Msk            (0x20UL)                  /*!< CH5OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH6OC_Pos            (6UL)                     /*!< CH6OC (Bit 6)                                         */
#define SPWM_SWOCTRL_CH6OC_Msk            (0x40UL)                  /*!< CH6OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH7OC_Pos            (7UL)                     /*!< CH7OC (Bit 7)                                         */
#define SPWM_SWOCTRL_CH7OC_Msk            (0x80UL)                  /*!< CH7OC (Bitfield-Mask: 0x01)                           */
#define SPWM_SWOCTRL_CH0OCV_Pos           (8UL)                     /*!< CH0OCV (Bit 8)                                        */
#define SPWM_SWOCTRL_CH0OCV_Msk           (0x100UL)                 /*!< CH0OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH1OCV_Pos           (9UL)                     /*!< CH1OCV (Bit 9)                                        */
#define SPWM_SWOCTRL_CH1OCV_Msk           (0x200UL)                 /*!< CH1OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH2OCV_Pos           (10UL)                    /*!< CH2OCV (Bit 10)                                       */
#define SPWM_SWOCTRL_CH2OCV_Msk           (0x400UL)                 /*!< CH2OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH3OCV_Pos           (11UL)                    /*!< CH3OCV (Bit 11)                                       */
#define SPWM_SWOCTRL_CH3OCV_Msk           (0x800UL)                 /*!< CH3OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH4OCV_Pos           (12UL)                    /*!< CH4OCV (Bit 12)                                       */
#define SPWM_SWOCTRL_CH4OCV_Msk           (0x1000UL)                /*!< CH4OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH5OCV_Pos           (13UL)                    /*!< CH5OCV (Bit 13)                                       */
#define SPWM_SWOCTRL_CH5OCV_Msk           (0x2000UL)                /*!< CH5OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH6OCV_Pos           (14UL)                    /*!< CH6OCV (Bit 14)                                       */
#define SPWM_SWOCTRL_CH6OCV_Msk           (0x4000UL)                /*!< CH6OCV (Bitfield-Mask: 0x01)                          */
#define SPWM_SWOCTRL_CH7OCV_Pos           (15UL)                    /*!< CH7OCV (Bit 15)                                       */
#define SPWM_SWOCTRL_CH7OCV_Msk           (0x8000UL)                /*!< CH7OCV (Bitfield-Mask: 0x01)                          */
/* =======================================================  DEADTIME0  ======================================================= */
#define SPWM_DEADTIME0_DTVAL0_Pos         (0UL)                     /*!< DTVAL0 (Bit 0)                                        */
#define SPWM_DEADTIME0_DTVAL0_Msk         (0x3ffUL)                 /*!< DTVAL0 (Bitfield-Mask: 0x3ff)                         */
#define SPWM_DEADTIME0_DTPS0_Pos          (12UL)                    /*!< DTPS0 (Bit 12)                                        */
#define SPWM_DEADTIME0_DTPS0_Msk          (0x3000UL)                /*!< DTPS0 (Bitfield-Mask: 0x03)                           */
#define SPWM_DEADTIME0_DTVAL1_Pos         (16UL)                    /*!< DTVAL1 (Bit 16)                                       */
#define SPWM_DEADTIME0_DTVAL1_Msk         (0x3ff0000UL)             /*!< DTVAL1 (Bitfield-Mask: 0x3ff)                         */
#define SPWM_DEADTIME0_DTPS1_Pos          (28UL)                    /*!< DTPS1 (Bit 28)                                        */
#define SPWM_DEADTIME0_DTPS1_Msk          (0x30000000UL)            /*!< DTPS1 (Bitfield-Mask: 0x03)                           */
/* =======================================================  DEADTIME1  ======================================================= */
#define SPWM_DEADTIME1_DTVAL2_Pos         (0UL)                     /*!< DTVAL2 (Bit 0)                                        */
#define SPWM_DEADTIME1_DTVAL2_Msk         (0x3ffUL)                 /*!< DTVAL2 (Bitfield-Mask: 0x3ff)                         */
#define SPWM_DEADTIME1_DTPS2_Pos          (12UL)                    /*!< DTPS2 (Bit 12)                                        */
#define SPWM_DEADTIME1_DTPS2_Msk          (0x3000UL)                /*!< DTPS2 (Bitfield-Mask: 0x03)                           */
#define SPWM_DEADTIME1_DTVAL3_Pos         (16UL)                    /*!< DTVAL3 (Bit 16)                                       */
#define SPWM_DEADTIME1_DTVAL3_Msk         (0x3ff0000UL)             /*!< DTVAL3 (Bitfield-Mask: 0x3ff)                         */
#define SPWM_DEADTIME1_DTPS3_Pos          (28UL)                    /*!< DTPS3 (Bit 28)                                        */
#define SPWM_DEADTIME1_DTPS3_Msk          (0x30000000UL)            /*!< DTPS3 (Bitfield-Mask: 0x03)                           */
/* =======================================================  CHDITHER0  ======================================================= */
#define SPWM_CH0DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH0DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH1DITHER  ======================================================= */
#define SPWM_CH1DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH1DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH2DITHER  ======================================================= */
#define SPWM_CH2DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH2DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH3DITHER  ======================================================= */
#define SPWM_CH3DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH3DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH4DITHER  ======================================================= */
#define SPWM_CH4DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH4DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH5DITHER  ======================================================= */
#define SPWM_CH5DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH5DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH6DITHER  ======================================================= */
#define SPWM_CH6DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH6DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  CH7DITHER  ======================================================= */
#define SPWM_CH7DITHER_CHDITHER_Pos       (0UL)                     /*!< CHDITHER (Bit 0)                                      */
#define SPWM_CH7DITHER_CHDITHER_Msk       (0x1fUL)                  /*!< CHDITHER (Bitfield-Mask: 0x1f)                        */
/* =======================================================  MODDITHER  ======================================================= */
#define SPWM_MODDITHER_MODDITHER_Pos      (0UL)                     /*!< MODDITHER (Bit 0)                                     */
#define SPWM_MODDITHER_MODDITHER_Msk      (0x1fUL)                  /*!< MODDITHER (Bitfield-Mask: 0x1f)                       */


/* =========================================================================================================================== */
/* ================                                           ADC                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  SR0  ========================================================== */
#define ADC_SR0_IDLE_Pos                  (0UL)                     /*!< IDLE (Bit 0)                                          */
#define ADC_SR0_IDLE_Msk                  (0x1UL)                   /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define ADC_SR0_PEOS_Pos                  (1UL)                     /*!< PEOS (Bit 1)                                          */
#define ADC_SR0_PEOS_Msk                  (0x2UL)                   /*!< PEOS (Bitfield-Mask: 0x01)                            */
#define ADC_SR0_NEOS_Pos                  (2UL)                     /*!< NEOS (Bit 2)                                          */
#define ADC_SR0_NEOS_Msk                  (0x4UL)                   /*!< NEOS (Bitfield-Mask: 0x01)                            */
#define ADC_SR0_PEOC0_Pos                 (8UL)                     /*!< PEOC0 (Bit 8)                                         */
#define ADC_SR0_PEOC0_Msk                 (0x100UL)                 /*!< PEOC0 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PEOC1_Pos                 (9UL)                     /*!< PEOC1 (Bit 9)                                         */
#define ADC_SR0_PEOC1_Msk                 (0x200UL)                 /*!< PEOC1 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PEOC2_Pos                 (10UL)                    /*!< PEOC2 (Bit 10)                                        */
#define ADC_SR0_PEOC2_Msk                 (0x400UL)                 /*!< PEOC2 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PEOC3_Pos                 (11UL)                    /*!< PEOC3 (Bit 11)                                        */
#define ADC_SR0_PEOC3_Msk                 (0x800UL)                 /*!< PEOC3 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PAWD0_Pos                 (12UL)                    /*!< PAWD0 (Bit 12)                                        */
#define ADC_SR0_PAWD0_Msk                 (0x1000UL)                /*!< PAWD0 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PAWD1_Pos                 (13UL)                    /*!< PAWD1 (Bit 13)                                        */
#define ADC_SR0_PAWD1_Msk                 (0x2000UL)                /*!< PAWD1 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PAWD2_Pos                 (14UL)                    /*!< PAWD2 (Bit 14)                                        */
#define ADC_SR0_PAWD2_Msk                 (0x4000UL)                /*!< PAWD2 (Bitfield-Mask: 0x01)                           */
#define ADC_SR0_PAWD3_Pos                 (15UL)                    /*!< PAWD3 (Bit 15)                                        */
#define ADC_SR0_PAWD3_Msk                 (0x8000UL)                /*!< PAWD3 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR1  ========================================================== */
#define ADC_SR1_NEOC0_Pos                 (0UL)                     /*!< NEOC0 (Bit 0)                                         */
#define ADC_SR1_NEOC0_Msk                 (0x1UL)                   /*!< NEOC0 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC1_Pos                 (1UL)                     /*!< NEOC1 (Bit 1)                                         */
#define ADC_SR1_NEOC1_Msk                 (0x2UL)                   /*!< NEOC1 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC2_Pos                 (2UL)                     /*!< NEOC2 (Bit 2)                                         */
#define ADC_SR1_NEOC2_Msk                 (0x4UL)                   /*!< NEOC2 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC3_Pos                 (3UL)                     /*!< NEOC3 (Bit 3)                                         */
#define ADC_SR1_NEOC3_Msk                 (0x8UL)                   /*!< NEOC3 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC4_Pos                 (4UL)                     /*!< NEOC4 (Bit 4)                                         */
#define ADC_SR1_NEOC4_Msk                 (0x10UL)                  /*!< NEOC4 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC5_Pos                 (5UL)                     /*!< NEOC5 (Bit 5)                                         */
#define ADC_SR1_NEOC5_Msk                 (0x20UL)                  /*!< NEOC5 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC6_Pos                 (6UL)                     /*!< NEOC6 (Bit 6)                                         */
#define ADC_SR1_NEOC6_Msk                 (0x40UL)                  /*!< NEOC6 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC7_Pos                 (7UL)                     /*!< NEOC7 (Bit 7)                                         */
#define ADC_SR1_NEOC7_Msk                 (0x80UL)                  /*!< NEOC7 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC8_Pos                 (8UL)                     /*!< NEOC8 (Bit 8)                                         */
#define ADC_SR1_NEOC8_Msk                 (0x100UL)                 /*!< NEOC8 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC9_Pos                 (9UL)                     /*!< NEOC9 (Bit 9)                                         */
#define ADC_SR1_NEOC9_Msk                 (0x200UL)                 /*!< NEOC9 (Bitfield-Mask: 0x01)                           */
#define ADC_SR1_NEOC10_Pos                (10UL)                    /*!< NEOC10 (Bit 10)                                       */
#define ADC_SR1_NEOC10_Msk                (0x400UL)                 /*!< NEOC10 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC11_Pos                (11UL)                    /*!< NEOC11 (Bit 11)                                       */
#define ADC_SR1_NEOC11_Msk                (0x800UL)                 /*!< NEOC11 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC12_Pos                (12UL)                    /*!< NEOC12 (Bit 12)                                       */
#define ADC_SR1_NEOC12_Msk                (0x1000UL)                /*!< NEOC12 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC13_Pos                (13UL)                    /*!< NEOC13 (Bit 13)                                       */
#define ADC_SR1_NEOC13_Msk                (0x2000UL)                /*!< NEOC13 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC14_Pos                (14UL)                    /*!< NEOC14 (Bit 14)                                       */
#define ADC_SR1_NEOC14_Msk                (0x4000UL)                /*!< NEOC14 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC15_Pos                (15UL)                    /*!< NEOC15 (Bit 15)                                       */
#define ADC_SR1_NEOC15_Msk                (0x8000UL)                /*!< NEOC15 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC16_Pos                (16UL)                    /*!< NEOC16 (Bit 16)                                       */
#define ADC_SR1_NEOC16_Msk                (0x10000UL)               /*!< NEOC16 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC17_Pos                (17UL)                    /*!< NEOC17 (Bit 17)                                       */
#define ADC_SR1_NEOC17_Msk                (0x20000UL)               /*!< NEOC17 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC18_Pos                (18UL)                    /*!< NEOC18 (Bit 18)                                       */
#define ADC_SR1_NEOC18_Msk                (0x40000UL)               /*!< NEOC18 (Bitfield-Mask: 0x01)                          */
#define ADC_SR1_NEOC19_Pos                (19UL)                    /*!< NEOC19 (Bit 19)                                       */
#define ADC_SR1_NEOC19_Msk                (0x80000UL)               /*!< NEOC19 (Bitfield-Mask: 0x01)                          */
/* ==========================================================  SR2  ========================================================== */
#define ADC_SR2_NAWD0_Pos                 (0UL)                     /*!< NAWD0 (Bit 0)                                         */
#define ADC_SR2_NAWD0_Msk                 (0x1UL)                   /*!< NAWD0 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD1_Pos                 (1UL)                     /*!< NAWD1 (Bit 1)                                         */
#define ADC_SR2_NAWD1_Msk                 (0x2UL)                   /*!< NAWD1 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD2_Pos                 (2UL)                     /*!< NAWD2 (Bit 2)                                         */
#define ADC_SR2_NAWD2_Msk                 (0x4UL)                   /*!< NAWD2 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD3_Pos                 (3UL)                     /*!< NAWD3 (Bit 3)                                         */
#define ADC_SR2_NAWD3_Msk                 (0x8UL)                   /*!< NAWD3 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD4_Pos                 (4UL)                     /*!< NAWD4 (Bit 4)                                         */
#define ADC_SR2_NAWD4_Msk                 (0x10UL)                  /*!< NAWD4 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD5_Pos                 (5UL)                     /*!< NAWD5 (Bit 5)                                         */
#define ADC_SR2_NAWD5_Msk                 (0x20UL)                  /*!< NAWD5 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD6_Pos                 (6UL)                     /*!< NAWD6 (Bit 6)                                         */
#define ADC_SR2_NAWD6_Msk                 (0x40UL)                  /*!< NAWD6 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD7_Pos                 (7UL)                     /*!< NAWD7 (Bit 7)                                         */
#define ADC_SR2_NAWD7_Msk                 (0x80UL)                  /*!< NAWD7 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD8_Pos                 (8UL)                     /*!< NAWD8 (Bit 8)                                         */
#define ADC_SR2_NAWD8_Msk                 (0x100UL)                 /*!< NAWD8 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD9_Pos                 (9UL)                     /*!< NAWD9 (Bit 9)                                         */
#define ADC_SR2_NAWD9_Msk                 (0x200UL)                 /*!< NAWD9 (Bitfield-Mask: 0x01)                           */
#define ADC_SR2_NAWD10_Pos                (10UL)                    /*!< NAWD10 (Bit 10)                                       */
#define ADC_SR2_NAWD10_Msk                (0x400UL)                 /*!< NAWD10 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD11_Pos                (11UL)                    /*!< NAWD11 (Bit 11)                                       */
#define ADC_SR2_NAWD11_Msk                (0x800UL)                 /*!< NAWD11 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD12_Pos                (12UL)                    /*!< NAWD12 (Bit 12)                                       */
#define ADC_SR2_NAWD12_Msk                (0x1000UL)                /*!< NAWD12 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD13_Pos                (13UL)                    /*!< NAWD13 (Bit 13)                                       */
#define ADC_SR2_NAWD13_Msk                (0x2000UL)                /*!< NAWD13 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD14_Pos                (14UL)                    /*!< NAWD14 (Bit 14)                                       */
#define ADC_SR2_NAWD14_Msk                (0x4000UL)                /*!< NAWD14 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD15_Pos                (15UL)                    /*!< NAWD15 (Bit 15)                                       */
#define ADC_SR2_NAWD15_Msk                (0x8000UL)                /*!< NAWD15 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD16_Pos                (16UL)                    /*!< NAWD16 (Bit 16)                                       */
#define ADC_SR2_NAWD16_Msk                (0x10000UL)               /*!< NAWD16 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD17_Pos                (17UL)                    /*!< NAWD17 (Bit 17)                                       */
#define ADC_SR2_NAWD17_Msk                (0x20000UL)               /*!< NAWD17 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD18_Pos                (18UL)                    /*!< NAWD18 (Bit 18)                                       */
#define ADC_SR2_NAWD18_Msk                (0x40000UL)               /*!< NAWD18 (Bitfield-Mask: 0x01)                          */
#define ADC_SR2_NAWD19_Pos                (19UL)                    /*!< NAWD19 (Bit 19)                                       */
#define ADC_SR2_NAWD19_Msk                (0x80000UL)               /*!< NAWD19 (Bitfield-Mask: 0x01)                          */
/* ==========================================================  CR0  ========================================================== */
#define ADC_CR0_ADON_Pos                  (0UL)                     /*!< ADON (Bit 0)                                          */
#define ADC_CR0_ADON_Msk                  (0x1UL)                   /*!< ADON (Bitfield-Mask: 0x01)                            */
#define ADC_CR0_PEXTTRIG_Pos              (1UL)                     /*!< PEXTTRIG (Bit 1)                                      */
#define ADC_CR0_PEXTTRIG_Msk              (0x2UL)                   /*!< PEXTTRIG (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_PSWSTART_Pos              (2UL)                     /*!< PSWSTART (Bit 2)                                      */
#define ADC_CR0_PSWSTART_Msk              (0x4UL)                   /*!< PSWSTART (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_NEXTTRIG_Pos              (3UL)                     /*!< NEXTTRIG (Bit 3)                                      */
#define ADC_CR0_NEXTTRIG_Msk              (0x8UL)                   /*!< NEXTTRIG (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_NSWSTART_Pos              (4UL)                     /*!< NSWSTART (Bit 4)                                      */
#define ADC_CR0_NSWSTART_Msk              (0x10UL)                  /*!< NSWSTART (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_DMAMODE_Pos               (5UL)                     /*!< DMAMODE (Bit 5)                                       */
#define ADC_CR0_DMAMODE_Msk               (0x60UL)                  /*!< DMAMODE (Bitfield-Mask: 0x03)                         */
#define ADC_CR0_AVGS_Pos                  (7UL)                     /*!< AVGS (Bit 7)                                          */
#define ADC_CR0_AVGS_Msk                  (0x180UL)                 /*!< AVGS (Bitfield-Mask: 0x03)                            */
#define ADC_CR0_AVGE_Pos                  (9UL)                     /*!< AVGE (Bit 9)                                          */
#define ADC_CR0_AVGE_Msk                  (0x200UL)                 /*!< AVGE (Bitfield-Mask: 0x01)                            */
#define ADC_CR0_CALE_Pos                  (10UL)                    /*!< CALE (Bit 10)                                         */
#define ADC_CR0_CALE_Msk                  (0x400UL)                 /*!< CALE (Bitfield-Mask: 0x01)                            */
#define ADC_CR0_SWSTOP_Pos                (11UL)                    /*!< SWSTOP (Bit 11)                                       */
#define ADC_CR0_SWSTOP_Msk                (0x800UL)                 /*!< SWSTOP (Bitfield-Mask: 0x01)                          */
#define ADC_CR0_PMODE_Pos                 (12UL)                    /*!< PMODE (Bit 12)                                        */
#define ADC_CR0_PMODE_Msk                 (0x3000UL)                /*!< PMODE (Bitfield-Mask: 0x03)                           */
#define ADC_CR0_NMODE_Pos                 (14UL)                    /*!< NMODE (Bit 14)                                        */
#define ADC_CR0_NMODE_Msk                 (0xc000UL)                /*!< NMODE (Bitfield-Mask: 0x03)                           */
#define ADC_CR0_PSQL_Pos                  (16UL)                    /*!< PSQL (Bit 16)                                         */
#define ADC_CR0_PSQL_Msk                  (0x30000UL)               /*!< PSQL (Bitfield-Mask: 0x03)                            */
#define ADC_CR0_NSQL_Pos                  (18UL)                    /*!< NSQL (Bit 18)                                         */
#define ADC_CR0_NSQL_Msk                  (0x7c0000UL)              /*!< NSQL (Bitfield-Mask: 0x1f)                            */
#define ADC_CR0_RES_Pos                   (23UL)                    /*!< RES (Bit 23)                                          */
#define ADC_CR0_RES_Msk                   (0x1800000UL)             /*!< RES (Bitfield-Mask: 0x03)                             */
#define ADC_CR0_VREFPSEL_Pos              (26UL)                    /*!< VREFPSEL (Bit 26)                                     */
#define ADC_CR0_VREFPSEL_Msk              (0x4000000UL)             /*!< VREFPSEL (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_VREFNSEL_Pos              (27UL)                    /*!< VREFNSEL (Bit 27)                                     */
#define ADC_CR0_VREFNSEL_Msk              (0x8000000UL)             /*!< VREFNSEL (Bitfield-Mask: 0x01)                        */
#define ADC_CR0_PEOSIE_Pos                (28UL)                    /*!< PEOSIE (Bit 28)                                       */
#define ADC_CR0_PEOSIE_Msk                (0x10000000UL)            /*!< PEOSIE (Bitfield-Mask: 0x01)                          */
#define ADC_CR0_NEOSIE_Pos                (29UL)                    /*!< NEOSIE (Bit 29)                                       */
#define ADC_CR0_NEOSIE_Msk                (0x20000000UL)            /*!< NEOSIE (Bitfield-Mask: 0x01)                          */
#define ADC_CR0_BUFEN_Pos                 (30UL)                    /*!< BUFEN (Bit 30)                                        */
#define ADC_CR0_BUFEN_Msk                 (0x40000000UL)            /*!< BUFEN (Bitfield-Mask: 0x01)                           */
#define ADC_CR0_BUFSEL_Pos                (31UL)                    /*!< BUFSEL (Bit 31)                                       */
#define ADC_CR0_BUFSEL_Msk                (0x80000000UL)            /*!< BUFSEL (Bitfield-Mask: 0x01)                          */
/* =========================================================  POFR0  ========================================================= */
#define ADC_POFR0_POFFSET_Pos             (0UL)                     /*!< POFFSET (Bit 0)                                       */
#define ADC_POFR0_POFFSET_Msk             (0xfffUL)                 /*!< POFFSET (Bitfield-Mask: 0xfff)                        */
/* =========================================================  POFR1  ========================================================= */
#define ADC_POFR1_POFFSET_Pos             (0UL)                     /*!< POFFSET (Bit 0)                                       */
#define ADC_POFR1_POFFSET_Msk             (0xfffUL)                 /*!< POFFSET (Bitfield-Mask: 0xfff)                        */
/* =========================================================  POFR2  ========================================================= */
#define ADC_POFR2_POFFSET_Pos             (0UL)                     /*!< POFFSET (Bit 0)                                       */
#define ADC_POFR2_POFFSET_Msk             (0xfffUL)                 /*!< POFFSET (Bitfield-Mask: 0xfff)                        */
/* =========================================================  POFR3  ========================================================= */
#define ADC_POFR3_POFFSET_Pos             (0UL)                     /*!< POFFSET (Bit 0)                                       */
#define ADC_POFR3_POFFSET_Msk             (0xfffUL)                 /*!< POFFSET (Bitfield-Mask: 0xfff)                        */
/* =========================================================  HTR0  ========================================================== */
#define ADC_HTR0_AWDHT_Pos                (0UL)                     /*!< AWDHT (Bit 0)                                         */
#define ADC_HTR0_AWDHT_Msk                (0xffffUL)                /*!< AWDHT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  HTR1  ========================================================== */
#define ADC_HTR1_AWDHT_Pos                (0UL)                     /*!< AWDHT (Bit 0)                                         */
#define ADC_HTR1_AWDHT_Msk                (0xffffUL)                /*!< AWDHT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  HTR2  ========================================================== */
#define ADC_HTR2_AWDHT_Pos                (0UL)                     /*!< AWDHT (Bit 0)                                         */
#define ADC_HTR2_AWDHT_Msk                (0xffffUL)                /*!< AWDHT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  HTR3  ========================================================== */
#define ADC_HTR3_AWDHT_Pos                (0UL)                     /*!< AWDHT (Bit 0)                                         */
#define ADC_HTR3_AWDHT_Msk                (0xffffUL)                /*!< AWDHT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  LTR0  ========================================================== */
#define ADC_LTR0_AWDLT_Pos                (0UL)                     /*!< AWDLT (Bit 0)                                         */
#define ADC_LTR0_AWDLT_Msk                (0xffffUL)                /*!< AWDLT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  LTR1  ========================================================== */
#define ADC_LTR1_AWDLT_Pos                (0UL)                     /*!< AWDLT (Bit 0)                                         */
#define ADC_LTR1_AWDLT_Msk                (0xffffUL)                /*!< AWDLT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  LTR2  ========================================================== */
#define ADC_LTR2_AWDLT_Pos                (0UL)                     /*!< AWDLT (Bit 0)                                         */
#define ADC_LTR2_AWDLT_Msk                (0xffffUL)                /*!< AWDLT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  LTR3  ========================================================== */
#define ADC_LTR3_AWDLT_Pos                (0UL)                     /*!< AWDLT (Bit 0)                                         */
#define ADC_LTR3_AWDLT_Msk                (0xffffUL)                /*!< AWDLT (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NSQR0  ========================================================= */
#define ADC_NSQR0_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR0_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR0_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR0_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR0_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR0_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR0_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR0_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR0_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR0_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR0_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR0_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR0_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR0_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR1  ========================================================= */
#define ADC_NSQR1_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR1_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR1_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR1_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR1_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR1_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR1_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR1_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR1_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR1_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR1_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR1_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR1_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR1_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR2  ========================================================= */
#define ADC_NSQR2_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR2_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR2_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR2_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR2_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR2_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR2_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR2_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR2_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR2_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR2_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR2_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR2_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR2_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR3  ========================================================= */
#define ADC_NSQR3_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR3_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR3_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR3_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR3_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR3_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR3_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR3_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR3_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR3_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR3_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR3_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR3_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR3_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR4  ========================================================= */
#define ADC_NSQR4_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR4_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR4_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR4_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR4_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR4_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR4_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR4_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR4_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR4_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR4_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR4_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR4_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR4_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR5  ========================================================= */
#define ADC_NSQR5_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR5_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR5_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR5_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR5_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR5_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR5_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR5_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR5_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR5_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR5_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR5_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR5_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR5_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR6  ========================================================= */
#define ADC_NSQR6_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR6_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR6_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR6_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR6_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR6_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR6_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR6_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR6_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR6_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR6_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR6_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR6_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR6_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR7  ========================================================= */
#define ADC_NSQR7_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR7_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR7_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR7_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR7_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR7_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR7_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR7_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR7_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR7_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR7_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR7_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR7_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR7_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR8  ========================================================= */
#define ADC_NSQR8_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR8_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR8_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR8_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR8_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR8_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR8_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR8_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR8_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR8_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR8_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR8_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR8_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR8_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NSQR9  ========================================================= */
#define ADC_NSQR9_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR9_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR9_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR9_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR9_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR9_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR9_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR9_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR9_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR9_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR9_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR9_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR9_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR9_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR10  ========================================================= */
#define ADC_NSQR10_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR10_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR10_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR10_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR10_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR10_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR10_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR10_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR10_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR10_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR10_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR10_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR10_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR10_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR11  ========================================================= */
#define ADC_NSQR11_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR11_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR11_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR11_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR11_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR11_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR11_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR11_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR11_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR11_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR11_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR11_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR11_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR11_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR12  ========================================================= */
#define ADC_NSQR12_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR12_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR12_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR12_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR12_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR12_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR12_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR12_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR12_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR12_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR12_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR12_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR12_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR12_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR13  ========================================================= */
#define ADC_NSQR13_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR13_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR13_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR13_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR13_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR13_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR13_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR13_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR13_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR13_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR13_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR13_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR13_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR13_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR14  ========================================================= */
#define ADC_NSQR14_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR14_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR14_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR14_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR14_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR14_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR14_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR14_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR14_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR14_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR14_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR14_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR14_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR14_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR15  ========================================================= */
#define ADC_NSQR15_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR15_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR15_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR15_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR15_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR15_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR15_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR15_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR15_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR15_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR15_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR15_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR15_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR15_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR16  ========================================================= */
#define ADC_NSQR16_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR16_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR16_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR16_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR16_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR16_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR16_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR16_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR16_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR16_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR16_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR16_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR16_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR16_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR17  ========================================================= */
#define ADC_NSQR17_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR17_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR17_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR17_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR17_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR17_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR17_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR17_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR17_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR17_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR17_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR17_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR17_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR17_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR18  ========================================================= */
#define ADC_NSQR18_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR18_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR18_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR18_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR18_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR18_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR18_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR18_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR18_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR18_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR18_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR18_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR18_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR18_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* ========================================================  NSQR19  ========================================================= */
#define ADC_NSQR19_CHSEL_Pos              (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_NSQR19_CHSEL_Msk              (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_NSQR19_SMP_Pos                (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_NSQR19_SMP_Msk                (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_NSQR19_AWDSEL_Pos             (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_NSQR19_AWDSEL_Msk             (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_NSQR19_AWDEN_Pos              (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_NSQR19_AWDEN_Msk              (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR19_AWDIE_Pos              (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_NSQR19_AWDIE_Msk              (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR19_EOCIE_Pos              (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_NSQR19_EOCIE_Msk              (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_NSQR19_AWDTRIGEN_Pos          (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_NSQR19_AWDTRIGEN_Msk          (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  PSQR0  ========================================================= */
#define ADC_PSQR0_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_PSQR0_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_PSQR0_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_PSQR0_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_PSQR0_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_PSQR0_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_PSQR0_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_PSQR0_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR0_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_PSQR0_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR0_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_PSQR0_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR0_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_PSQR0_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  PSQR1  ========================================================= */
#define ADC_PSQR1_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_PSQR1_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_PSQR1_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_PSQR1_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_PSQR1_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_PSQR1_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_PSQR1_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_PSQR1_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR1_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_PSQR1_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR1_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_PSQR1_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR1_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_PSQR1_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  PSQR2  ========================================================= */
#define ADC_PSQR2_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_PSQR2_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_PSQR2_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_PSQR2_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_PSQR2_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_PSQR2_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_PSQR2_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_PSQR2_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR2_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_PSQR2_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR2_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_PSQR2_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR2_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_PSQR2_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  PSQR3  ========================================================= */
#define ADC_PSQR3_CHSEL_Pos               (0UL)                     /*!< CHSEL (Bit 0)                                         */
#define ADC_PSQR3_CHSEL_Msk               (0x3fUL)                  /*!< CHSEL (Bitfield-Mask: 0x3f)                           */
#define ADC_PSQR3_SMP_Pos                 (6UL)                     /*!< SMP (Bit 6)                                           */
#define ADC_PSQR3_SMP_Msk                 (0x1c0UL)                 /*!< SMP (Bitfield-Mask: 0x07)                             */
#define ADC_PSQR3_AWDSEL_Pos              (9UL)                     /*!< AWDSEL (Bit 9)                                        */
#define ADC_PSQR3_AWDSEL_Msk              (0x600UL)                 /*!< AWDSEL (Bitfield-Mask: 0x03)                          */
#define ADC_PSQR3_AWDEN_Pos               (11UL)                    /*!< AWDEN (Bit 11)                                        */
#define ADC_PSQR3_AWDEN_Msk               (0x800UL)                 /*!< AWDEN (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR3_AWDIE_Pos               (12UL)                    /*!< AWDIE (Bit 12)                                        */
#define ADC_PSQR3_AWDIE_Msk               (0x1000UL)                /*!< AWDIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR3_EOCIE_Pos               (13UL)                    /*!< EOCIE (Bit 13)                                        */
#define ADC_PSQR3_EOCIE_Msk               (0x2000UL)                /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_PSQR3_AWDTRIGEN_Pos           (14UL)                    /*!< AWDTRIGEN (Bit 14)                                    */
#define ADC_PSQR3_AWDTRIGEN_Msk           (0x4000UL)                /*!< AWDTRIGEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  NDR0  ========================================================== */
#define ADC_NDR0_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR0_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR1  ========================================================== */
#define ADC_NDR1_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR1_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR2  ========================================================== */
#define ADC_NDR2_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR2_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR3  ========================================================== */
#define ADC_NDR3_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR3_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR4  ========================================================== */
#define ADC_NDR4_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR4_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR5  ========================================================== */
#define ADC_NDR5_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR5_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR6  ========================================================== */
#define ADC_NDR6_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR6_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR7  ========================================================== */
#define ADC_NDR7_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR7_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR8  ========================================================== */
#define ADC_NDR8_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR8_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR9  ========================================================== */
#define ADC_NDR9_NDATA_Pos                (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR9_NDATA_Msk                (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR10  ========================================================= */
#define ADC_NDR10_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR10_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR11  ========================================================= */
#define ADC_NDR11_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR11_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR12  ========================================================= */
#define ADC_NDR12_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR12_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR13  ========================================================= */
#define ADC_NDR13_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR13_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR14  ========================================================= */
#define ADC_NDR14_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR14_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR15  ========================================================= */
#define ADC_NDR15_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR15_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR16  ========================================================= */
#define ADC_NDR16_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR16_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR17  ========================================================= */
#define ADC_NDR17_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR17_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR18  ========================================================= */
#define ADC_NDR18_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR18_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  NDR19  ========================================================= */
#define ADC_NDR19_NDATA_Pos               (0UL)                     /*!< NDATA (Bit 0)                                         */
#define ADC_NDR19_NDATA_Msk               (0xfffUL)                 /*!< NDATA (Bitfield-Mask: 0xfff)                          */
/* =========================================================  PDR0  ========================================================== */
#define ADC_PDR0_PDATA_Pos                (0UL)                     /*!< PDATA (Bit 0)                                         */
#define ADC_PDR0_PDATA_Msk                (0xffffUL)                /*!< PDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  PDR1  ========================================================== */
#define ADC_PDR1_PDATA_Pos                (0UL)                     /*!< PDATA (Bit 0)                                         */
#define ADC_PDR1_PDATA_Msk                (0xffffUL)                /*!< PDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  PDR2  ========================================================== */
#define ADC_PDR2_PDATA_Pos                (0UL)                     /*!< PDATA (Bit 0)                                         */
#define ADC_PDR2_PDATA_Msk                (0xffffUL)                /*!< PDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  PDR3  ========================================================== */
#define ADC_PDR3_PDATA_Pos                (0UL)                     /*!< PDATA (Bit 0)                                         */
#define ADC_PDR3_PDATA_Msk                (0xffffUL)                /*!< PDATA (Bitfield-Mask: 0xffff)                         */


/* =========================================================================================================================== */
/* ================                                            ICM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define ICM_CR0_ADC0_NTRIG_SEL0_Pos       (0UL)                     /*!< ADC0_NTRIG_SEL0 (Bit 0)                               */
#define ICM_CR0_ADC0_NTRIG_SEL0_Msk       (0x1fUL)                  /*!< ADC0_NTRIG_SEL0 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR0_ADC0_NTRIG_SEL1_Pos       (5UL)                     /*!< ADC0_NTRIG_SEL1 (Bit 5)                               */
#define ICM_CR0_ADC0_NTRIG_SEL1_Msk       (0x3e0UL)                 /*!< ADC0_NTRIG_SEL1 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR0_ADC0_NTRIG_SEL2_Pos       (10UL)                    /*!< ADC0_NTRIG_SEL2 (Bit 10)                              */
#define ICM_CR0_ADC0_NTRIG_SEL2_Msk       (0x7c00UL)                /*!< ADC0_NTRIG_SEL2 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR0_ADC0_NTRIG_SEL3_Pos       (15UL)                    /*!< ADC0_NTRIG_SEL3 (Bit 15)                              */
#define ICM_CR0_ADC0_NTRIG_SEL3_Msk       (0xf8000UL)               /*!< ADC0_NTRIG_SEL3 (Bitfield-Mask: 0x1f)                 */
/* ==========================================================  CR1  ========================================================== */
#define ICM_CR1_ADC0_PTRIG_SEL0_Pos       (0UL)                     /*!< ADC0_PTRIG_SEL0 (Bit 0)                               */
#define ICM_CR1_ADC0_PTRIG_SEL0_Msk       (0x1fUL)                  /*!< ADC0_PTRIG_SEL0 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR1_ADC0_PTRIG_SEL1_Pos       (5UL)                     /*!< ADC0_PTRIG_SEL1 (Bit 5)                               */
#define ICM_CR1_ADC0_PTRIG_SEL1_Msk       (0x3e0UL)                 /*!< ADC0_PTRIG_SEL1 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR1_ADC0_PTRIG_SEL2_Pos       (10UL)                    /*!< ADC0_PTRIG_SEL2 (Bit 10)                              */
#define ICM_CR1_ADC0_PTRIG_SEL2_Msk       (0x7c00UL)                /*!< ADC0_PTRIG_SEL2 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR1_ADC0_PTRIG_SEL3_Pos       (15UL)                    /*!< ADC0_PTRIG_SEL3 (Bit 15)                              */
#define ICM_CR1_ADC0_PTRIG_SEL3_Msk       (0xf8000UL)               /*!< ADC0_PTRIG_SEL3 (Bitfield-Mask: 0x1f)                 */
/* ==========================================================  CR2  ========================================================== */
#define ICM_CR2_ADC1_NTRIG_SEL0_Pos       (0UL)                     /*!< ADC1_NTRIG_SEL0 (Bit 0)                               */
#define ICM_CR2_ADC1_NTRIG_SEL0_Msk       (0x1fUL)                  /*!< ADC1_NTRIG_SEL0 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR2_ADC1_NTRIG_SEL1_Pos       (5UL)                     /*!< ADC1_NTRIG_SEL1 (Bit 5)                               */
#define ICM_CR2_ADC1_NTRIG_SEL1_Msk       (0x3e0UL)                 /*!< ADC1_NTRIG_SEL1 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR2_ADC1_NTRIG_SEL2_Pos       (10UL)                    /*!< ADC1_NTRIG_SEL2 (Bit 10)                              */
#define ICM_CR2_ADC1_NTRIG_SEL2_Msk       (0x7c00UL)                /*!< ADC1_NTRIG_SEL2 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR2_ADC1_NTRIG_SEL3_Pos       (15UL)                    /*!< ADC1_NTRIG_SEL3 (Bit 15)                              */
#define ICM_CR2_ADC1_NTRIG_SEL3_Msk       (0xf8000UL)               /*!< ADC1_NTRIG_SEL3 (Bitfield-Mask: 0x1f)                 */
/* ==========================================================  CR3  ========================================================== */
#define ICM_CR3_ADC1_PTRIG_SEL0_Pos       (0UL)                     /*!< ADC1_PTRIG_SEL0 (Bit 0)                               */
#define ICM_CR3_ADC1_PTRIG_SEL0_Msk       (0x1fUL)                  /*!< ADC1_PTRIG_SEL0 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR3_ADC1_PTRIG_SEL1_Pos       (5UL)                     /*!< ADC1_PTRIG_SEL1 (Bit 5)                               */
#define ICM_CR3_ADC1_PTRIG_SEL1_Msk       (0x3e0UL)                 /*!< ADC1_PTRIG_SEL1 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR3_ADC1_PTRIG_SEL2_Pos       (10UL)                    /*!< ADC1_PTRIG_SEL2 (Bit 10)                              */
#define ICM_CR3_ADC1_PTRIG_SEL2_Msk       (0x7c00UL)                /*!< ADC1_PTRIG_SEL2 (Bitfield-Mask: 0x1f)                 */
#define ICM_CR3_ADC1_PTRIG_SEL3_Pos       (15UL)                    /*!< ADC1_PTRIG_SEL3 (Bit 15)                              */
#define ICM_CR3_ADC1_PTRIG_SEL3_Msk       (0xf8000UL)               /*!< ADC1_PTRIG_SEL3 (Bitfield-Mask: 0x1f)                 */
/* ==========================================================  CR4  ========================================================== */
#define ICM_CR4_SPWM0_FAULT2_SEL_Pos      (0UL)                     /*!< SPWM0_FAULT2_SEL (Bit 0)                              */
#define ICM_CR4_SPWM0_FAULT2_SEL_Msk      (0x3UL)                   /*!< SPWM0_FAULT2_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM0_FAULT3_SEL_Pos      (2UL)                     /*!< SPWM0_FAULT3_SEL (Bit 2)                              */
#define ICM_CR4_SPWM0_FAULT3_SEL_Msk      (0xcUL)                   /*!< SPWM0_FAULT3_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM1_FAULT2_SEL_Pos      (4UL)                     /*!< SPWM1_FAULT2_SEL (Bit 4)                              */
#define ICM_CR4_SPWM1_FAULT2_SEL_Msk      (0x30UL)                  /*!< SPWM1_FAULT2_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM1_FAULT3_SEL_Pos      (6UL)                     /*!< SPWM1_FAULT3_SEL (Bit 6)                              */
#define ICM_CR4_SPWM1_FAULT3_SEL_Msk      (0xc0UL)                  /*!< SPWM1_FAULT3_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM2_FAULT2_SEL_Pos      (8UL)                     /*!< SPWM2_FAULT2_SEL (Bit 8)                              */
#define ICM_CR4_SPWM2_FAULT2_SEL_Msk      (0x300UL)                 /*!< SPWM2_FAULT2_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM2_FAULT3_SEL_Pos      (10UL)                    /*!< SPWM2_FAULT3_SEL (Bit 10)                             */
#define ICM_CR4_SPWM2_FAULT3_SEL_Msk      (0xc00UL)                 /*!< SPWM2_FAULT3_SEL (Bitfield-Mask: 0x03)                */
#define ICM_CR4_SPWM0_SYNC0_SEL_Pos       (12UL)                    /*!< SPWM0_SYNC0_SEL (Bit 12)                              */
#define ICM_CR4_SPWM0_SYNC0_SEL_Msk       (0x1000UL)                /*!< SPWM0_SYNC0_SEL (Bitfield-Mask: 0x01)                 */
#define ICM_CR4_SPWM0_SYNC1_SEL_Pos       (13UL)                    /*!< SPWM0_SYNC1_SEL (Bit 13)                              */
#define ICM_CR4_SPWM0_SYNC1_SEL_Msk       (0x2000UL)                /*!< SPWM0_SYNC1_SEL (Bitfield-Mask: 0x01)                 */
#define ICM_CR4_SPWM1_SYNC0_SEL_Pos       (14UL)                    /*!< SPWM1_SYNC0_SEL (Bit 14)                              */
#define ICM_CR4_SPWM1_SYNC0_SEL_Msk       (0x4000UL)                /*!< SPWM1_SYNC0_SEL (Bitfield-Mask: 0x01)                 */
#define ICM_CR4_SPWM1_SYNC1_SEL_Pos       (15UL)                    /*!< SPWM1_SYNC1_SEL (Bit 15)                              */
#define ICM_CR4_SPWM1_SYNC1_SEL_Msk       (0x8000UL)                /*!< SPWM1_SYNC1_SEL (Bitfield-Mask: 0x01)                 */
#define ICM_CR4_SPWM0_OUT0_SEL_Pos        (16UL)                    /*!< SPWM0_OUT0_SEL (Bit 16)                               */
#define ICM_CR4_SPWM0_OUT0_SEL_Msk        (0x10000UL)               /*!< SPWM0_OUT0_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT1_SEL_Pos        (17UL)                    /*!< SPWM0_OUT1_SEL (Bit 17)                               */
#define ICM_CR4_SPWM0_OUT1_SEL_Msk        (0x20000UL)               /*!< SPWM0_OUT1_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT2_SEL_Pos        (18UL)                    /*!< SPWM0_OUT2_SEL (Bit 18)                               */
#define ICM_CR4_SPWM0_OUT2_SEL_Msk        (0x40000UL)               /*!< SPWM0_OUT2_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT3_SEL_Pos        (19UL)                    /*!< SPWM0_OUT3_SEL (Bit 19)                               */
#define ICM_CR4_SPWM0_OUT3_SEL_Msk        (0x80000UL)               /*!< SPWM0_OUT3_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT4_SEL_Pos        (20UL)                    /*!< SPWM0_OUT4_SEL (Bit 20)                               */
#define ICM_CR4_SPWM0_OUT4_SEL_Msk        (0x100000UL)              /*!< SPWM0_OUT4_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT5_SEL_Pos        (21UL)                    /*!< SPWM0_OUT5_SEL (Bit 21)                               */
#define ICM_CR4_SPWM0_OUT5_SEL_Msk        (0x200000UL)              /*!< SPWM0_OUT5_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT6_SEL_Pos        (22UL)                    /*!< SPWM0_OUT6_SEL (Bit 22)                               */
#define ICM_CR4_SPWM0_OUT6_SEL_Msk        (0x400000UL)              /*!< SPWM0_OUT6_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM0_OUT7_SEL_Pos        (23UL)                    /*!< SPWM0_OUT7_SEL (Bit 23)                               */
#define ICM_CR4_SPWM0_OUT7_SEL_Msk        (0x800000UL)              /*!< SPWM0_OUT7_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT0_SEL_Pos        (24UL)                    /*!< SPWM1_OUT0_SEL (Bit 24)                               */
#define ICM_CR4_SPWM1_OUT0_SEL_Msk        (0x1000000UL)             /*!< SPWM1_OUT0_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT1_SEL_Pos        (25UL)                    /*!< SPWM1_OUT1_SEL (Bit 25)                               */
#define ICM_CR4_SPWM1_OUT1_SEL_Msk        (0x2000000UL)             /*!< SPWM1_OUT1_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT2_SEL_Pos        (26UL)                    /*!< SPWM1_OUT2_SEL (Bit 26)                               */
#define ICM_CR4_SPWM1_OUT2_SEL_Msk        (0x4000000UL)             /*!< SPWM1_OUT2_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT3_SEL_Pos        (27UL)                    /*!< SPWM1_OUT3_SEL (Bit 27)                               */
#define ICM_CR4_SPWM1_OUT3_SEL_Msk        (0x8000000UL)             /*!< SPWM1_OUT3_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT4_SEL_Pos        (28UL)                    /*!< SPWM1_OUT4_SEL (Bit 28)                               */
#define ICM_CR4_SPWM1_OUT4_SEL_Msk        (0x10000000UL)            /*!< SPWM1_OUT4_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT5_SEL_Pos        (29UL)                    /*!< SPWM1_OUT5_SEL (Bit 29)                               */
#define ICM_CR4_SPWM1_OUT5_SEL_Msk        (0x20000000UL)            /*!< SPWM1_OUT5_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT6_SEL_Pos        (30UL)                    /*!< SPWM1_OUT6_SEL (Bit 30)                               */
#define ICM_CR4_SPWM1_OUT6_SEL_Msk        (0x40000000UL)            /*!< SPWM1_OUT6_SEL (Bitfield-Mask: 0x01)                  */
#define ICM_CR4_SPWM1_OUT7_SEL_Pos        (31UL)                    /*!< SPWM1_OUT7_SEL (Bit 31)                               */
#define ICM_CR4_SPWM1_OUT7_SEL_Msk        (0x80000000UL)            /*!< SPWM1_OUT7_SEL (Bitfield-Mask: 0x01)                  */
/* ==========================================================  CR5  ========================================================== */
#define ICM_CR5_SPWM0_CAP_PAE_Pos         (0UL)                     /*!< SPWM0_CAP_PAE (Bit 0)                                 */
#define ICM_CR5_SPWM0_CAP_PAE_Msk         (0x1UL)                   /*!< SPWM0_CAP_PAE (Bitfield-Mask: 0x01)                   */
#define ICM_CR5_SPWM1_CAP_PAE_Pos         (1UL)                     /*!< SPWM1_CAP_PAE (Bit 1)                                 */
#define ICM_CR5_SPWM1_CAP_PAE_Msk         (0x2UL)                   /*!< SPWM1_CAP_PAE (Bitfield-Mask: 0x01)                   */
#define ICM_CR5_SPWM2_CAP_PAE_Pos         (2UL)                     /*!< SPWM2_CAP_PAE (Bit 2)                                 */
#define ICM_CR5_SPWM2_CAP_PAE_Msk         (0x4UL)                   /*!< SPWM2_CAP_PAE (Bitfield-Mask: 0x01)                   */
#define ICM_CR5_IPWM0_CAP0_SEL_Pos        (3UL)                     /*!< IPWM0_CAP0_SEL (Bit 3)                                */
#define ICM_CR5_IPWM0_CAP0_SEL_Msk        (0x18UL)                  /*!< IPWM0_CAP0_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM0_CAP1_SEL_Pos        (5UL)                     /*!< IPWM0_CAP1_SEL (Bit 5)                                */
#define ICM_CR5_IPWM0_CAP1_SEL_Msk        (0x60UL)                  /*!< IPWM0_CAP1_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM0_CAP2_SEL_Pos        (7UL)                     /*!< IPWM0_CAP2_SEL (Bit 7)                                */
#define ICM_CR5_IPWM0_CAP2_SEL_Msk        (0x180UL)                 /*!< IPWM0_CAP2_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM0_CAP3_SEL_Pos        (9UL)                     /*!< IPWM0_CAP3_SEL (Bit 9)                                */
#define ICM_CR5_IPWM0_CAP3_SEL_Msk        (0x600UL)                 /*!< IPWM0_CAP3_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM1_CAP0_SEL_Pos        (11UL)                    /*!< IPWM1_CAP0_SEL (Bit 11)                               */
#define ICM_CR5_IPWM1_CAP0_SEL_Msk        (0x1800UL)                /*!< IPWM1_CAP0_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM1_CAP1_SEL_Pos        (13UL)                    /*!< IPWM1_CAP1_SEL (Bit 13)                               */
#define ICM_CR5_IPWM1_CAP1_SEL_Msk        (0x6000UL)                /*!< IPWM1_CAP1_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM1_CAP2_SEL_Pos        (15UL)                    /*!< IPWM1_CAP2_SEL (Bit 15)                               */
#define ICM_CR5_IPWM1_CAP2_SEL_Msk        (0x18000UL)               /*!< IPWM1_CAP2_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_IPWM1_CAP3_SEL_Pos        (17UL)                    /*!< IPWM1_CAP3_SEL (Bit 17)                               */
#define ICM_CR5_IPWM1_CAP3_SEL_Msk        (0x60000UL)               /*!< IPWM1_CAP3_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_CMP_WINDOW_SEL_Pos        (19UL)                    /*!< CMP_WINDOW_SEL (Bit 19)                               */
#define ICM_CR5_CMP_WINDOW_SEL_Msk        (0x180000UL)              /*!< CMP_WINDOW_SEL (Bitfield-Mask: 0x03)                  */
#define ICM_CR5_SPWM2_SYNC0_SEL_Pos       (21UL)                    /*!< SPWM2_SYNC0_SEL (Bit 21)                              */
#define ICM_CR5_SPWM2_SYNC0_SEL_Msk       (0x200000UL)              /*!< SPWM2_SYNC0_SEL (Bitfield-Mask: 0x01)                 */
#define ICM_CR5_SPWM2_SYNC1_SEL_Pos       (22UL)                    /*!< SPWM2_SYNC1_SEL (Bit 22)                              */
#define ICM_CR5_SPWM2_SYNC1_SEL_Msk       (0x400000UL)              /*!< SPWM2_SYNC1_SEL (Bitfield-Mask: 0x01)                 */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define RTC_CFG_COSEL_Pos                 (0UL)                     /*!< COSEL (Bit 0)                                         */
#define RTC_CFG_COSEL_Msk                 (0x1UL)                   /*!< COSEL (Bitfield-Mask: 0x01)                           */
#define RTC_CFG_COEN_Pos                  (1UL)                     /*!< COEN (Bit 1)                                          */
#define RTC_CFG_COEN_Msk                  (0x2UL)                   /*!< COEN (Bitfield-Mask: 0x01)                            */
#define RTC_CFG_RTCEN_Pos                 (8UL)                     /*!< RTCEN (Bit 8)                                         */
#define RTC_CFG_RTCEN_Msk                 (0x100UL)                 /*!< RTCEN (Bitfield-Mask: 0x01)                           */
#define RTC_CFG_ALMEN_Pos                 (9UL)                     /*!< ALMEN (Bit 9)                                         */
#define RTC_CFG_ALMEN_Msk                 (0x200UL)                 /*!< ALMEN (Bitfield-Mask: 0x01)                           */
#define RTC_CFG_PALMEN_Pos                (10UL)                    /*!< PALMEN (Bit 10)                                       */
#define RTC_CFG_PALMEN_Msk                (0x400UL)                 /*!< PALMEN (Bitfield-Mask: 0x01)                          */
#define RTC_CFG_TRIGEN_Pos                (11UL)                    /*!< TRIGEN (Bit 11)                                       */
#define RTC_CFG_TRIGEN_Msk                (0x800UL)                 /*!< TRIGEN (Bitfield-Mask: 0x01)                          */
#define RTC_CFG_CLKSEL_Pos                (13UL)                    /*!< CLKSEL (Bit 13)                                       */
#define RTC_CFG_CLKSEL_Msk                (0x6000UL)                /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
/* ==========================================================  ALM  ========================================================== */
#define RTC_ALM_ALM_Pos                   (0UL)                     /*!< ALM (Bit 0)                                           */
#define RTC_ALM_ALM_Msk                   (0xffffffffUL)            /*!< ALM (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  PALM  ========================================================== */
#define RTC_PALM_PALM_Pos                 (0UL)                     /*!< PALM (Bit 0)                                          */
#define RTC_PALM_PALM_Msk                 (0xffffffffUL)            /*!< PALM (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  PSCAL  ========================================================= */
#define RTC_PSCAL_PSCAL_Pos               (0UL)                     /*!< PSCAL (Bit 0)                                         */
#define RTC_PSCAL_PSCAL_Msk               (0xffffUL)                /*!< PSCAL (Bitfield-Mask: 0xffff)                         */
/* =========================================================  ICOMP  ========================================================= */
#define RTC_ICOMP_COMP_Pos                (0UL)                     /*!< COMP (Bit 0)                                          */
#define RTC_ICOMP_COMP_Msk                (0xffUL)                  /*!< COMP (Bitfield-Mask: 0xff)                            */
#define RTC_ICOMP_INR_Pos                 (8UL)                     /*!< INR (Bit 8)                                           */
#define RTC_ICOMP_INR_Msk                 (0xff00UL)                /*!< INR (Bitfield-Mask: 0xff)                             */
#define RTC_ICOMP_COMPCV_Pos              (16UL)                    /*!< COMPCV (Bit 16)                                       */
#define RTC_ICOMP_COMPCV_Msk              (0xff0000UL)              /*!< COMPCV (Bitfield-Mask: 0xff)                          */
#define RTC_ICOMP_INRCV_Pos               (24UL)                    /*!< INRCV (Bit 24)                                        */
#define RTC_ICOMP_INRCV_Msk               (0xff000000UL)            /*!< INRCV (Bitfield-Mask: 0xff)                           */
/* ==========================================================  INT  ========================================================== */
#define RTC_INT_ALMIEN_Pos                (0UL)                     /*!< ALMIEN (Bit 0)                                        */
#define RTC_INT_ALMIEN_Msk                (0x1UL)                   /*!< ALMIEN (Bitfield-Mask: 0x01)                          */
#define RTC_INT_PALMIEN_Pos               (1UL)                     /*!< PALMIEN (Bit 1)                                       */
#define RTC_INT_PALMIEN_Msk               (0x2UL)                   /*!< PALMIEN (Bitfield-Mask: 0x01)                         */
#define RTC_INT_SCOFIEN_Pos               (2UL)                     /*!< SCOFIEN (Bit 2)                                       */
#define RTC_INT_SCOFIEN_Msk               (0x4UL)                   /*!< SCOFIEN (Bitfield-Mask: 0x01)                         */
/* ========================================================  STATUS  ========================================================= */
#define RTC_STATUS_ALMF_Pos               (0UL)                     /*!< ALMF (Bit 0)                                          */
#define RTC_STATUS_ALMF_Msk               (0x1UL)                   /*!< ALMF (Bitfield-Mask: 0x01)                            */
#define RTC_STATUS_PALMF_Pos              (1UL)                     /*!< PALMF (Bit 1)                                         */
#define RTC_STATUS_PALMF_Msk              (0x2UL)                   /*!< PALMF (Bitfield-Mask: 0x01)                           */
#define RTC_STATUS_SCOFF_Pos              (2UL)                     /*!< SCOFF (Bit 2)                                         */
#define RTC_STATUS_SCOFF_Msk              (0x4UL)                   /*!< SCOFF (Bitfield-Mask: 0x01)                           */
#define RTC_STATUS_ALMNW_Pos              (8UL)                     /*!< ALMNW (Bit 8)                                         */
#define RTC_STATUS_ALMNW_Msk              (0x100UL)                 /*!< ALMNW (Bitfield-Mask: 0x01)                           */
#define RTC_STATUS_PALMNW_Pos             (9UL)                     /*!< PALMNW (Bit 9)                                        */
#define RTC_STATUS_PALMNW_Msk             (0x200UL)                 /*!< PALMNW (Bitfield-Mask: 0x01)                          */
#define RTC_STATUS_SCNTWF_Pos             (10UL)                    /*!< SCNTWF (Bit 10)                                       */
#define RTC_STATUS_SCNTWF_Msk             (0x400UL)                 /*!< SCNTWF (Bitfield-Mask: 0x01)                          */
/* =========================================================  SCNT  ========================================================== */
#define RTC_SCNT_SCNT_Pos                 (0UL)                     /*!< SCNT (Bit 0)                                          */
#define RTC_SCNT_SCNT_Msk                 (0xffffffffUL)            /*!< SCNT (Bitfield-Mask: 0xffffffff)                      */

/* =========================================================================================================================== */
/* ================                                            WDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CS  =========================================================== */
#define WDG_CS_UPDATE_Pos                 (5UL)                     /*!< UPDATE (Bit 5)                                        */
#define WDG_CS_UPDATE_Msk                 (0x20UL)                  /*!< UPDATE (Bitfield-Mask: 0x01)                          */
#define WDG_CS_INT_Pos                    (6UL)                     /*!< INT (Bit 6)                                           */
#define WDG_CS_INT_Msk                    (0x40UL)                  /*!< INT (Bitfield-Mask: 0x01)                             */
#define WDG_CS_EN_Pos                     (7UL)                     /*!< EN (Bit 7)                                            */
#define WDG_CS_EN_Msk                     (0x80UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define WDG_CS_CLK_Pos                    (8UL)                     /*!< CLK (Bit 8)                                           */
#define WDG_CS_CLK_Msk                    (0x100UL)                 /*!< CLK (Bitfield-Mask: 0x01)                             */
#define WDG_CS_RCS_Pos                    (10UL)                    /*!< RCS (Bit 10)                                          */
#define WDG_CS_RCS_Msk                    (0x400UL)                 /*!< RCS (Bitfield-Mask: 0x01)                             */
#define WDG_CS_LOCK_Pos                   (11UL)                    /*!< LOCK (Bit 11)                                         */
#define WDG_CS_LOCK_Msk                   (0x800UL)                 /*!< LOCK (Bitfield-Mask: 0x01)                            */
#define WDG_CS_PRES_Pos                   (12UL)                    /*!< PRES (Bit 12)                                         */
#define WDG_CS_PRES_Msk                   (0x1000UL)                /*!< PRES (Bitfield-Mask: 0x01)                            */
#define WDG_CS_FLG_Pos                    (14UL)                    /*!< FLG (Bit 14)                                          */
#define WDG_CS_FLG_Msk                    (0x4000UL)                /*!< FLG (Bitfield-Mask: 0x01)                             */
#define WDG_CS_WIN_Pos                    (15UL)                    /*!< WIN (Bit 15)                                          */
#define WDG_CS_WIN_Msk                    (0x8000UL)                /*!< WIN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CNT  ========================================================== */
#define WDG_CNT_VAL_Pos                   (0UL)                     /*!< VAL (Bit 0)                                           */
#define WDG_CNT_VAL_Msk                   (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* =========================================================  TOVAL  ========================================================= */
#define WDG_TOVAL_VAL_Pos                 (0UL)                     /*!< VAL (Bit 0)                                           */
#define WDG_TOVAL_VAL_Msk                 (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  WIN  ========================================================== */
#define WDG_WIN_VAL_Pos                   (0UL)                     /*!< VAL (Bit 0)                                           */
#define WDG_WIN_VAL_Msk                   (0xffffUL)                /*!< VAL (Bitfield-Mask: 0xffff)                           */

/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  SR  =========================================================== */
#define FLASH_SR_CCF_Pos                  (0UL)                     /*!< CCF (Bit 0)                                           */
#define FLASH_SR_CCF_Msk                  (0x1UL)                   /*!< CCF (Bitfield-Mask: 0x01)                             */
#define FLASH_SR_ACCERR_Pos               (1UL)                     /*!< ACCERR (Bit 1)                                        */
#define FLASH_SR_ACCERR_Msk               (0x2UL)                   /*!< ACCERR (Bitfield-Mask: 0x01)                          */
#define FLASH_SR_CMDERR_Pos               (2UL)                     /*!< CMDERR (Bit 2)                                        */
#define FLASH_SR_CMDERR_Msk               (0x4UL)                   /*!< CMDERR (Bitfield-Mask: 0x01)                          */
#define FLASH_SR_WPVIO_Pos                (6UL)                     /*!< WPVIO (Bit 6)                                         */
#define FLASH_SR_WPVIO_Msk                (0x40UL)                  /*!< WPVIO (Bitfield-Mask: 0x01)                           */
#define FLASH_SR_OPTERR_Pos               (7UL)                     /*!< OPTERR (Bit 7)                                        */
#define FLASH_SR_OPTERR_Msk               (0x80UL)                  /*!< OPTERR (Bitfield-Mask: 0x01)                          */
/* =========================================================  LCSR  ========================================================== */
#define FLASH_LCSR_MID_Pos                (0UL)                     /*!< MID (Bit 0)                                           */
#define FLASH_LCSR_MID_Msk                (0x3UL)                   /*!< MID (Bitfield-Mask: 0x03)                             */
#define FLASH_LCSR_OLCS_Pos               (29UL)                    /*!< OLCS (Bit 29)                                         */
#define FLASH_LCSR_OLCS_Msk               (0x20000000UL)            /*!< OLCS (Bitfield-Mask: 0x01)                            */
#define FLASH_LCSR_DLCS_Pos               (30UL)                    /*!< DLCS (Bit 30)                                         */
#define FLASH_LCSR_DLCS_Msk               (0x40000000UL)            /*!< DLCS (Bitfield-Mask: 0x01)                            */
#define FLASH_LCSR_PLCS_Pos               (31UL)                    /*!< PLCS (Bit 31)                                         */
#define FLASH_LCSR_PLCS_Msk               (0x80000000UL)            /*!< PLCS (Bitfield-Mask: 0x01)                            */
/* =========================================================  PKEY  ========================================================== */
#define FLASH_PKEY_PKEY_Pos               (0UL)                     /*!< PKEY (Bit 0)                                          */
#define FLASH_PKEY_PKEY_Msk               (0xffffffffUL)            /*!< PKEY (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DKEY  ========================================================== */
#define FLASH_DKEY_DKEY_Pos               (0UL)                     /*!< DKEY (Bit 0)                                          */
#define FLASH_DKEY_DKEY_Msk               (0xffffffffUL)            /*!< DKEY (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  OKEY  ========================================================== */
#define FLASH_OKEY_OKEY_Pos               (0UL)                     /*!< OKEY (Bit 0)                                          */
#define FLASH_OKEY_OKEY_Msk               (0xffffffffUL)            /*!< OKEY (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  CFGR  ========================================================== */
#define FLASH_CFGR_PCACHEEN_Pos           (0UL)                     /*!< PCACHEEN (Bit 0)                                      */
#define FLASH_CFGR_PCACHEEN_Msk           (0x1UL)                   /*!< PCACHEEN (Bitfield-Mask: 0x01)                        */
#define FLASH_CFGR_PCACHECLR_Pos          (1UL)                     /*!< PCACHECLR (Bit 1)                                     */
#define FLASH_CFGR_PCACHECLR_Msk          (0x2UL)                   /*!< PCACHECLR (Bitfield-Mask: 0x01)                       */
#define FLASH_CFGR_DCACHEEN_Pos           (2UL)                     /*!< DCACHEEN (Bit 2)                                      */
#define FLASH_CFGR_DCACHEEN_Msk           (0x4UL)                   /*!< DCACHEEN (Bitfield-Mask: 0x01)                        */
#define FLASH_CFGR_DCACHECLR_Pos          (3UL)                     /*!< DCACHECLR (Bit 3)                                     */
#define FLASH_CFGR_DCACHECLR_Msk          (0x8UL)                   /*!< DCACHECLR (Bitfield-Mask: 0x01)                       */
#define FLASH_CFGR_PPREEN_Pos             (4UL)                     /*!< PPREEN (Bit 4)                                        */
#define FLASH_CFGR_PPREEN_Msk             (0x10UL)                  /*!< PPREEN (Bitfield-Mask: 0x01)                          */
#define FLASH_CFGR_DPREEN_Pos             (5UL)                     /*!< DPREEN (Bit 5)                                        */
#define FLASH_CFGR_DPREEN_Msk             (0x20UL)                  /*!< DPREEN (Bitfield-Mask: 0x01)                          */
#define FLASH_CFGR_FREQ_Pos               (16UL)                    /*!< FREQ (Bit 16)                                         */
#define FLASH_CFGR_FREQ_Msk               (0xffff0000UL)            /*!< FREQ (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  CCR  ========================================================== */
#define FLASH_CCR_CMD_Pos                 (0UL)                     /*!< CMD (Bit 0)                                           */
#define FLASH_CCR_CMD_Msk                 (0xfUL)                   /*!< CMD (Bitfield-Mask: 0x0f)                             */
#define FLASH_CCR_PGLEN_Pos               (24UL)                    /*!< PGLEN (Bit 24)                                        */
#define FLASH_CCR_PGLEN_Msk               (0xff000000UL)            /*!< PGLEN (Bitfield-Mask: 0xff)                           */
/* =========================================================  ADDR  ========================================================== */
#define FLASH_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define FLASH_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DATAH  ========================================================= */
#define FLASH_DATAH_DATAH_Pos             (0UL)                     /*!< DATAH (Bit 0)                                         */
#define FLASH_DATAH_DATAH_Msk             (0xffffffffUL)            /*!< DATAH (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DATAL  ========================================================= */
#define FLASH_DATAL_DATAL_Pos             (0UL)                     /*!< DATAL (Bit 0)                                         */
#define FLASH_DATAL_DATAL_Msk             (0xffffffffUL)            /*!< DATAL (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  PDBCR  ========================================================= */
#define FLASH_PDBCR_FLUSH_Pos             (31UL)                    /*!< FLUSH (Bit 31)                                        */
#define FLASH_PDBCR_FLUSH_Msk             (0x80000000UL)            /*!< FLUSH (Bitfield-Mask: 0x01)                           */
/* =========================================================  MACR  ========================================================== */
#define FLASH_MACR_MACKEY_Pos             (0UL)                     /*!< MACKEY (Bit 0)                                        */
#define FLASH_MACR_MACKEY_Msk             (0xffffffffUL)            /*!< MACKEY (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  ABSSR  ========================================================= */
#define FLASH_ABSSR_SWAPEN_Pos            (0UL)                     /*!< SWAPEN (Bit 0)                                        */
#define FLASH_ABSSR_SWAPEN_Msk            (0x1UL)                   /*!< SWAPEN (Bitfield-Mask: 0x01)                          */
#define FLASH_ABSSR_SWAPSEL_Pos           (1UL)                     /*!< SWAPSEL (Bit 1)                                       */
#define FLASH_ABSSR_SWAPSEL_Msk           (0x2UL)                   /*!< SWAPSEL (Bitfield-Mask: 0x01)                         */
/* =========================================================  DBGPR  ========================================================= */
#define FLASH_DBGPR_DBGPEN_Pos            (0UL)                     /*!< DBGPEN (Bit 0)                                        */
#define FLASH_DBGPR_DBGPEN_Msk            (0x1UL)                   /*!< DBGPEN (Bitfield-Mask: 0x01)                          */
#define FLASH_DBGPR_DBGAUTS_Pos           (1UL)                     /*!< DBGAUTS (Bit 1)                                       */
#define FLASH_DBGPR_DBGAUTS_Msk           (0x2UL)                   /*!< DBGAUTS (Bitfield-Mask: 0x01)                         */
#define FLASH_DBGPR_DBGENS_Pos            (2UL)                     /*!< DBGENS (Bit 2)                                        */
#define FLASH_DBGPR_DBGENS_Msk            (0x4UL)                   /*!< DBGENS (Bitfield-Mask: 0x01)                          */
#define FLASH_DBGPR_DBGAUT_Pos            (31UL)                    /*!< DBGAUT (Bit 31)                                       */
#define FLASH_DBGPR_DBGAUT_Msk            (0x80000000UL)            /*!< DBGAUT (Bitfield-Mask: 0x01)                          */
/* ========================================================  DBGKEY0  ======================================================== */
#define FLASH_DBGKEY0_DBGKEY0_Pos         (0UL)                     /*!< DBGKEY0 (Bit 0)                                       */
#define FLASH_DBGKEY0_DBGKEY0_Msk         (0xffffffffUL)            /*!< DBGKEY0 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY1  ======================================================== */
#define FLASH_DBGKEY1_DBGKEY1_Pos         (0UL)                     /*!< DBGKEY1 (Bit 0)                                       */
#define FLASH_DBGKEY1_DBGKEY1_Msk         (0xffffffffUL)            /*!< DBGKEY1 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY2  ======================================================== */
#define FLASH_DBGKEY2_DBGKEY2_Pos         (0UL)                     /*!< DBGKEY2 (Bit 0)                                       */
#define FLASH_DBGKEY2_DBGKEY2_Msk         (0xffffffffUL)            /*!< DBGKEY2 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY3  ======================================================== */
#define FLASH_DBGKEY3_DBGKEY3_Pos         (0UL)                     /*!< DBGKEY3 (Bit 0)                                       */
#define FLASH_DBGKEY3_DBGKEY3_Msk         (0xffffffffUL)            /*!< DBGKEY3 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY4  ======================================================== */
#define FLASH_DBGKEY4_DBGKEY4_Pos         (0UL)                     /*!< DBGKEY4 (Bit 0)                                       */
#define FLASH_DBGKEY4_DBGKEY4_Msk         (0xffffffffUL)            /*!< DBGKEY4 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY5  ======================================================== */
#define FLASH_DBGKEY5_DBGKEY5_Pos         (0UL)                     /*!< DBGKEY5 (Bit 0)                                       */
#define FLASH_DBGKEY5_DBGKEY5_Msk         (0xffffffffUL)            /*!< DBGKEY5 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY6  ======================================================== */
#define FLASH_DBGKEY6_DBGKEY6_Pos         (0UL)                     /*!< DBGKEY6 (Bit 0)                                       */
#define FLASH_DBGKEY6_DBGKEY6_Msk         (0xffffffffUL)            /*!< DBGKEY6 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DBGKEY7  ======================================================== */
#define FLASH_DBGKEY7_DBGKEY7_Pos         (0UL)                     /*!< DBGKEY7 (Bit 0)                                       */
#define FLASH_DBGKEY7_DBGKEY7_Msk         (0xffffffffUL)            /*!< DBGKEY7 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  P0WPR0  ========================================================= */
#define FLASH_P0WPR0_P0WPR0_Pos           (0UL)                     /*!< P0WPR0 (Bit 0)                                        */
#define FLASH_P0WPR0_P0WPR0_Msk           (0xffffffffUL)            /*!< P0WPR0 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR1  ========================================================= */
#define FLASH_P0WPR1_P0WPR1_Pos           (0UL)                     /*!< P0WPR1 (Bit 0)                                        */
#define FLASH_P0WPR1_P0WPR1_Msk           (0xffffffffUL)            /*!< P0WPR1 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR2  ========================================================= */
#define FLASH_P0WPR2_P0WPR2_Pos           (0UL)                     /*!< P0WPR2 (Bit 0)                                        */
#define FLASH_P0WPR2_P0WPR2_Msk           (0xffffffffUL)            /*!< P0WPR2 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR3  ========================================================= */
#define FLASH_P0WPR3_P0WPR3_Pos           (0UL)                     /*!< P0WPR3 (Bit 0)                                        */
#define FLASH_P0WPR3_P0WPR3_Msk           (0xffffffffUL)            /*!< P0WPR3 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR4  ========================================================= */
#define FLASH_P0WPR4_P0WPR4_Pos           (0UL)                     /*!< P0WPR4 (Bit 0)                                        */
#define FLASH_P0WPR4_P0WPR4_Msk           (0xffffffffUL)            /*!< P0WPR4 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR5  ========================================================= */
#define FLASH_P0WPR5_P0WPR5_Pos           (0UL)                     /*!< P0WPR5 (Bit 0)                                        */
#define FLASH_P0WPR5_P0WPR5_Msk           (0xffffffffUL)            /*!< P0WPR5 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR6  ========================================================= */
#define FLASH_P0WPR6_P0WPR6_Pos           (0UL)                     /*!< P0WPR6 (Bit 0)                                        */
#define FLASH_P0WPR6_P0WPR6_Msk           (0xffffffffUL)            /*!< P0WPR6 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P0WPR7  ========================================================= */
#define FLASH_P0WPR7_P0WPR7_Pos           (0UL)                     /*!< P0WPR7 (Bit 0)                                        */
#define FLASH_P0WPR7_P0WPR7_Msk           (0xffffffffUL)            /*!< P0WPR7 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR0  ========================================================= */
#define FLASH_P1WPR0_P1WPR0_Pos           (0UL)                     /*!< P1WPR0 (Bit 0)                                        */
#define FLASH_P1WPR0_P1WPR0_Msk           (0xffffffffUL)            /*!< P1WPR0 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR1  ========================================================= */
#define FLASH_P1WPR1_P1WPR1_Pos           (0UL)                     /*!< P1WPR1 (Bit 0)                                        */
#define FLASH_P1WPR1_P1WPR1_Msk           (0xffffffffUL)            /*!< P1WPR1 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR2  ========================================================= */
#define FLASH_P1WPR2_P1WPR2_Pos           (0UL)                     /*!< P1WPR2 (Bit 0)                                        */
#define FLASH_P1WPR2_P1WPR2_Msk           (0xffffffffUL)            /*!< P1WPR2 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR3  ========================================================= */
#define FLASH_P1WPR3_P1WPR3_Pos           (0UL)                     /*!< P1WPR3 (Bit 0)                                        */
#define FLASH_P1WPR3_P1WPR3_Msk           (0xffffffffUL)            /*!< P1WPR3 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR4  ========================================================= */
#define FLASH_P1WPR4_P1WPR4_Pos           (0UL)                     /*!< P1WPR4 (Bit 0)                                        */
#define FLASH_P1WPR4_P1WPR4_Msk           (0xffffffffUL)            /*!< P1WPR4 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR5  ========================================================= */
#define FLASH_P1WPR5_P1WPR5_Pos           (0UL)                     /*!< P1WPR5 (Bit 0)                                        */
#define FLASH_P1WPR5_P1WPR5_Msk           (0xffffffffUL)            /*!< P1WPR5 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR6  ========================================================= */
#define FLASH_P1WPR6_P1WPR6_Pos           (0UL)                     /*!< P1WPR6 (Bit 0)                                        */
#define FLASH_P1WPR6_P1WPR6_Msk           (0xffffffffUL)            /*!< P1WPR6 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  P1WPR7  ========================================================= */
#define FLASH_P1WPR7_P1WPR7_Pos           (0UL)                     /*!< P1WPR7 (Bit 0)                                        */
#define FLASH_P1WPR7_P1WPR7_Msk           (0xffffffffUL)            /*!< P1WPR7 (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  DWPR0  ========================================================= */
#define FLASH_DWPR0_DWPR0_Pos             (0UL)                     /*!< DWPR0 (Bit 0)                                         */
#define FLASH_DWPR0_DWPR0_Msk             (0xffffffffUL)            /*!< DWPR0 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DWPR1  ========================================================= */
#define FLASH_DWPR1_DWPR1_Pos             (0UL)                     /*!< DWPR1 (Bit 0)                                         */
#define FLASH_DWPR1_DWPR1_Msk             (0xffffffffUL)            /*!< DWPR1 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DWPR2  ========================================================= */
#define FLASH_DWPR2_DWPR2_Pos             (0UL)                     /*!< DWPR2 (Bit 0)                                         */
#define FLASH_DWPR2_DWPR2_Msk             (0xffffffffUL)            /*!< DWPR2 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DWPR3  ========================================================= */
#define FLASH_DWPR3_DWPR3_Pos             (0UL)                     /*!< DWPR3 (Bit 0)                                         */
#define FLASH_DWPR3_DWPR3_Msk             (0xffffffffUL)            /*!< DWPR3 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  UUID0  ========================================================= */
#define FLASH_UUID0_UUID0_Pos             (0UL)                     /*!< UUID0 (Bit 0)                                         */
#define FLASH_UUID0_UUID0_Msk             (0xffffffffUL)            /*!< UUID0 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  UUID1  ========================================================= */
#define FLASH_UUID1_UUID1_Pos             (0UL)                     /*!< UUID1 (Bit 0)                                         */
#define FLASH_UUID1_UUID1_Msk             (0xffffffffUL)            /*!< UUID1 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  UUID2  ========================================================= */
#define FLASH_UUID2_UUID2_Pos             (0UL)                     /*!< UUID2 (Bit 0)                                         */
#define FLASH_UUID2_UUID2_Msk             (0xffffffffUL)            /*!< UUID2 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  UUID3  ========================================================= */
#define FLASH_UUID3_UUID3_Pos             (0UL)                     /*!< UUID3 (Bit 0)                                         */
#define FLASH_UUID3_UUID3_Msk             (0xffffffffUL)            /*!< UUID3 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  CMNR  ========================================================== */
#define FLASH_CMNR_CMNR_Pos               (0UL)                     /*!< CMNR (Bit 0)                                          */
#define FLASH_CMNR_CMNR_Msk               (0xffffUL)                /*!< CMNR (Bitfield-Mask: 0xffff)                          */
#define FLASH_CMNR_BGOF_Pos               (16UL)                    /*!< BGOF (Bit 16)                                         */
#define FLASH_CMNR_BGOF_Msk               (0xffff0000UL)            /*!< BGOF (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CMIR  ========================================================== */
#define FLASH_CMIR_FSIZE_Pos              (0UL)                     /*!< FSIZE (Bit 0)                                         */
#define FLASH_CMIR_FSIZE_Msk              (0xffffUL)                /*!< FSIZE (Bitfield-Mask: 0xffff)                         */
#define FLASH_CMIR_SSIZE_Pos              (16UL)                    /*!< SSIZE (Bit 16)                                        */
#define FLASH_CMIR_SSIZE_Msk              (0xffff0000UL)            /*!< SSIZE (Bitfield-Mask: 0xffff)                         */
/* =========================================================  CPIR  ========================================================== */
#define FLASH_CPIR_CPIR_Pos               (0UL)                     /*!< CPIR (Bit 0)                                          */
#define FLASH_CPIR_CPIR_Msk               (0xffffffffUL)            /*!< CPIR (Bitfield-Mask: 0xffffffff)                      */

/* =========================================================================================================================== */
/* ================                                           I2C                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  BCR  ========================================================== */
#define I2C_BCR_SPW_Pos                  (0UL)                     /*!< SPW (Bit 0)                                           */
#define I2C_BCR_SPW_Msk                  (0xffUL)                  /*!< SPW (Bitfield-Mask: 0xff)                             */
#define I2C_BCR_PRSCA_Pos                (8UL)                     /*!< PRSCA (Bit 8)                                         */
#define I2C_BCR_PRSCA_Msk                (0xff00UL)                /*!< PRSCA (Bitfield-Mask: 0xff)                           */
/* =========================================================  SADDR  ========================================================= */
#define I2C_SADDR_ADDR0_Pos              (1UL)                     /*!< ADDR0 (Bit 1)                                         */
#define I2C_SADDR_ADDR0_Msk              (0x7feUL)                 /*!< ADDR0 (Bitfield-Mask: 0x3ff)                          */
#define I2C_SADDR_ADDR1_Pos              (17UL)                    /*!< ADDR1 (Bit 17)                                        */
#define I2C_SADDR_ADDR1_Msk              (0x7fe0000UL)             /*!< ADDR1 (Bitfield-Mask: 0x3ff)                          */
/* ==========================================================  CR  =========================================================== */
#define I2C_CR_IICEN_Pos                 (0UL)                     /*!< IICEN (Bit 0)                                         */
#define I2C_CR_IICEN_Msk                 (0x1UL)                   /*!< IICEN (Bitfield-Mask: 0x01)                           */
#define I2C_CR_MSSEL_Pos                 (1UL)                     /*!< MSSEL (Bit 1)                                         */
#define I2C_CR_MSSEL_Msk                 (0x2UL)                   /*!< MSSEL (Bitfield-Mask: 0x01)                           */
#define I2C_CR_STREN_Pos                 (2UL)                     /*!< STREN (Bit 2)                                         */
#define I2C_CR_STREN_Msk                 (0x4UL)                   /*!< STREN (Bitfield-Mask: 0x01)                           */
#define I2C_CR_CLKSYCEN_Pos              (3UL)                     /*!< CLKSYCEN (Bit 3)                                      */
#define I2C_CR_CLKSYCEN_Msk              (0x8UL)                   /*!< CLKSYCEN (Bitfield-Mask: 0x01)                        */
#define I2C_CR_MTXDIR_Pos                (4UL)                     /*!< MTXDIR (Bit 4)                                        */
#define I2C_CR_MTXDIR_Msk                (0x10UL)                  /*!< MTXDIR (Bitfield-Mask: 0x01)                          */
#define I2C_CR_RACK_Pos                  (5UL)                     /*!< RACK (Bit 5)                                          */
#define I2C_CR_RACK_Msk                  (0x20UL)                  /*!< RACK (Bitfield-Mask: 0x01)                            */
#define I2C_CR_RST_Pos                   (6UL)                     /*!< RST (Bit 6)                                           */
#define I2C_CR_RST_Msk                   (0x40UL)                  /*!< RST (Bitfield-Mask: 0x01)                             */
#define I2C_CR_ARBEN_Pos                 (7UL)                     /*!< ARBEN (Bit 7)                                         */
#define I2C_CR_ARBEN_Msk                 (0x80UL)                  /*!< ARBEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ICR  ========================================================== */
#define I2C_ICR_STARTIE_Pos              (0UL)                     /*!< STARTIE (Bit 0)                                       */
#define I2C_ICR_STARTIE_Msk              (0x1UL)                   /*!< STARTIE (Bitfield-Mask: 0x01)                         */
#define I2C_ICR_STOPIE_Pos               (1UL)                     /*!< STOPIE (Bit 1)                                        */
#define I2C_ICR_STOPIE_Msk               (0x2UL)                   /*!< STOPIE (Bitfield-Mask: 0x01)                          */
#define I2C_ICR_SAMIE_Pos                (2UL)                     /*!< SAMIE (Bit 2)                                         */
#define I2C_ICR_SAMIE_Msk                (0x4UL)                   /*!< SAMIE (Bitfield-Mask: 0x01)                           */
#define I2C_ICR_BTFIE_Pos                (3UL)                     /*!< BTFIE (Bit 3)                                         */
#define I2C_ICR_BTFIE_Msk                (0x8UL)                   /*!< BTFIE (Bitfield-Mask: 0x01)                           */
#define I2C_ICR_ARBLIE_Pos               (4UL)                     /*!< ARBLIE (Bit 4)                                        */
#define I2C_ICR_ARBLIE_Msk               (0x10UL)                  /*!< ARBLIE (Bitfield-Mask: 0x01)                          */
#define I2C_ICR_TXEIE_Pos                (5UL)                     /*!< TXEIE (Bit 5)                                         */
#define I2C_ICR_TXEIE_Msk                (0x20UL)                  /*!< TXEIE (Bitfield-Mask: 0x01)                           */
#define I2C_ICR_RXFIE_Pos                (6UL)                     /*!< RXFIE (Bit 6)                                         */
#define I2C_ICR_RXFIE_Msk                (0x40UL)                  /*!< RXFIE (Bitfield-Mask: 0x01)                           */
#define I2C_ICR_TXUFIE_Pos               (7UL)                     /*!< TXUFIE (Bit 7)                                        */
#define I2C_ICR_TXUFIE_Msk               (0x80UL)                  /*!< TXUFIE (Bitfield-Mask: 0x01)                          */
#define I2C_ICR_RXOFIE_Pos               (8UL)                     /*!< RXOFIE (Bit 8)                                        */
#define I2C_ICR_RXOFIE_Msk               (0x100UL)                 /*!< RXOFIE (Bitfield-Mask: 0x01)                          */
#define I2C_ICR_NACKIE_Pos               (9UL)                     /*!< NACKIE (Bit 9)                                        */
#define I2C_ICR_NACKIE_Msk               (0x200UL)                 /*!< NACKIE (Bitfield-Mask: 0x01)                          */
#define I2C_ICR_LTOIE_Pos                (10UL)                    /*!< LTOIE (Bit 10)                                        */
#define I2C_ICR_LTOIE_Msk                (0x400UL)                 /*!< LTOIE (Bitfield-Mask: 0x01)                           */
/* =========================================================  SAMC  ========================================================== */
#define I2C_SAMC_SADDM_Pos               (0UL)                     /*!< SADDM (Bit 0)                                         */
#define I2C_SAMC_SADDM_Msk               (0x1UL)                   /*!< SADDM (Bitfield-Mask: 0x01)                           */
#define I2C_SAMC_SRAEN_Pos               (1UL)                     /*!< SRAEN (Bit 1)                                         */
#define I2C_SAMC_SRAEN_Msk               (0x2UL)                   /*!< SRAEN (Bitfield-Mask: 0x01)                           */
#define I2C_SAMC_SGCAEN_Pos              (2UL)                     /*!< SGCAEN (Bit 2)                                        */
#define I2C_SAMC_SGCAEN_Msk              (0x4UL)                   /*!< SGCAEN (Bitfield-Mask: 0x01)                          */
#define I2C_SAMC_SAAEN_Pos               (3UL)                     /*!< SAAEN (Bit 3)                                         */
#define I2C_SAMC_SAAEN_Msk               (0x8UL)                   /*!< SAAEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  DER  ========================================================== */
#define I2C_DER_RDEN_Pos                 (0UL)                     /*!< RDEN (Bit 0)                                          */
#define I2C_DER_RDEN_Msk                 (0x1UL)                   /*!< RDEN (Bitfield-Mask: 0x01)                            */
#define I2C_DER_TDEN_Pos                 (1UL)                     /*!< TDEN (Bit 1)                                          */
#define I2C_DER_TDEN_Msk                 (0x2UL)                   /*!< TDEN (Bitfield-Mask: 0x01)                            */
#define I2C_DER_ACKE_Pos                 (2UL)                     /*!< ACKE (Bit 2)                                          */
#define I2C_DER_ACKE_Msk                 (0x4UL)                   /*!< ACKE (Bitfield-Mask: 0x01)                            */
#define I2C_DER_DTS_Pos                  (3UL)                     /*!< DTS (Bit 3)                                           */
#define I2C_DER_DTS_Msk                  (0x7ff8UL)                /*!< DTS (Bitfield-Mask: 0xfff)                            */
/* =========================================================  LTDR  ========================================================== */
#define I2C_LTDR_LTDSEL_Pos              (0UL)                     /*!< LTDSEL (Bit 0)                                        */
#define I2C_LTDR_LTDSEL_Msk              (0x1UL)                   /*!< LTDSEL (Bitfield-Mask: 0x01)                          */
#define I2C_LTDR_LTTV_Pos                (1UL)                     /*!< LTTV (Bit 1)                                          */
#define I2C_LTDR_LTTV_Msk                (0x3ffeUL)                /*!< LTTV (Bitfield-Mask: 0x1fff)                          */
/* =========================================================  DFCR  ========================================================== */
#define I2C_DFCR_DFW_Pos                 (0UL)                     /*!< DFW (Bit 0)                                           */
#define I2C_DFCR_DFW_Msk                 (0xfUL)                   /*!< DFW (Bitfield-Mask: 0x0f)                             */
/* =========================================================  MCMDR  ========================================================= */
#define I2C_MCMDR_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
#define I2C_MCMDR_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
#define I2C_MCMDR_STOP_Pos               (1UL)                     /*!< STOP (Bit 1)                                          */
#define I2C_MCMDR_STOP_Msk               (0x2UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2C_MCMDR_READ_Pos               (2UL)                     /*!< READ (Bit 2)                                          */
#define I2C_MCMDR_READ_Msk               (0x4UL)                   /*!< READ (Bitfield-Mask: 0x01)                            */
/* ==========================================================  SR0  ========================================================== */
#define I2C_SR0_STARTF_Pos               (0UL)                     /*!< STARTF (Bit 0)                                        */
#define I2C_SR0_STARTF_Msk               (0x1UL)                   /*!< STARTF (Bitfield-Mask: 0x01)                          */
#define I2C_SR0_STOPF_Pos                (1UL)                     /*!< STOPF (Bit 1)                                         */
#define I2C_SR0_STOPF_Msk                (0x2UL)                   /*!< STOPF (Bitfield-Mask: 0x01)                           */
#define I2C_SR0_SAMF_Pos                 (2UL)                     /*!< SAMF (Bit 2)                                          */
#define I2C_SR0_SAMF_Msk                 (0x4UL)                   /*!< SAMF (Bitfield-Mask: 0x01)                            */
#define I2C_SR0_BTF_Pos                  (3UL)                     /*!< BTF (Bit 3)                                          */
#define I2C_SR0_BTF_Msk                  (0x8UL)                   /*!< BTF (Bitfield-Mask: 0x01)                            */
#define I2C_SR0_ARBLF_Pos                (4UL)                     /*!< ARBLF (Bit 4)                                         */
#define I2C_SR0_ARBLF_Msk                (0x10UL)                  /*!< ARBLF (Bitfield-Mask: 0x01)                           */
#define I2C_SR0_TXEF_Pos                 (5UL)                     /*!< TXEF (Bit 5)                                          */
#define I2C_SR0_TXEF_Msk                 (0x20UL)                  /*!< TXEF (Bitfield-Mask: 0x01)                            */
#define I2C_SR0_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
#define I2C_SR0_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
#define I2C_SR0_TXUFF_Pos                (7UL)                     /*!< TXUFF (Bit 7)                                         */
#define I2C_SR0_TXUFF_Msk                (0x80UL)                  /*!< TXUFF (Bitfield-Mask: 0x01)                           */
#define I2C_SR0_RXOFF_Pos                (8UL)                     /*!< RXOFF (Bit 8)                                         */
#define I2C_SR0_RXOFF_Msk                (0x100UL)                 /*!< RXOFF (Bitfield-Mask: 0x01)                           */
#define I2C_SR0_NACKF_Pos                (9UL)                     /*!< NACKF (Bit 9)                                         */
#define I2C_SR0_NACKF_Msk                (0x200UL)                 /*!< NACKF (Bitfield-Mask: 0x01)                           */
#define I2C_SR0_LTOF_Pos                 (10UL)                    /*!< LTOF (Bit 10)                                        */
#define I2C_SR0_LTOF_Msk                 (0x400UL)                 /*!< LTOF (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR1  ========================================================== */
#define I2C_SR1_STRD_Pos                 (0UL)                     /*!< STRD (Bit 0)                                          */
#define I2C_SR1_STRD_Msk                 (0x1UL)                   /*!< STRD (Bitfield-Mask: 0x01)                            */
#define I2C_SR1_MRDY_Pos                 (1UL)                     /*!< MRDY (Bit 1)                                          */
#define I2C_SR1_MRDY_Msk                 (0x2UL)                   /*!< MRDY (Bitfield-Mask: 0x01)                            */
#define I2C_SR1_IDLE_Pos                 (2UL)                     /*!< IDLE (Bit 2)                                          */
#define I2C_SR1_IDLE_Msk                 (0x4UL)                   /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define I2C_SR1_GCMF_Pos                 (3UL)                     /*!< GCMF (Bit 3)                                          */
#define I2C_SR1_GCMF_Msk                 (0x8UL)                   /*!< GCMF (Bitfield-Mask: 0x01)                            */
#define I2C_SR1_ALMF_Pos                 (4UL)                     /*!< ALMF (Bit 4)                                          */
#define I2C_SR1_ALMF_Msk                 (0x10UL)                  /*!< ALMF (Bitfield-Mask: 0x01)                            */
/* =========================================================  DATA  ========================================================== */
#define I2C_DATA_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2C_DATA_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */


/* =========================================================================================================================== */
/* ================                                          TIMER                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define TIMER_CR_TEN_Pos                  (0UL)                     /*!< TEN (Bit 0)                                           */
#define TIMER_CR_TEN_Msk                  (0x1UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
#define TIMER_CR_TIE_Pos                  (1UL)                     /*!< TIE (Bit 1)                                           */
#define TIMER_CR_TIE_Msk                  (0x2UL)                   /*!< TIE (Bitfield-Mask: 0x01)                             */
/* =========================================================  PSCR  ========================================================== */
#define TIMER_PSCR_PSCVAL_Pos             (0UL)                     /*!< PSCVAL (Bit 0)                                        */
#define TIMER_PSCR_PSCVAL_Msk             (0xffUL)                  /*!< PSCVAL (Bitfield-Mask: 0xff)                          */
/* =========================================================  CMPR  ========================================================== */
#define TIMER_CMPR_CMPVAL_Pos             (0UL)                     /*!< CMPVAL (Bit 0)                                        */
#define TIMER_CMPR_CMPVAL_Msk             (0xffffffffUL)            /*!< CMPVAL (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  CNTR  ========================================================== */
#define TIMER_CNTR_CNTVAL_Pos             (0UL)                     /*!< CNTVAL (Bit 0)                                        */
#define TIMER_CNTR_CNTVAL_Msk             (0xffffffffUL)            /*!< CNTVAL (Bitfield-Mask: 0xffffffff)                    */
/* ==========================================================  SR  =========================================================== */
#define TIMER_SR_CMPF_Pos                 (0UL)                     /*!< CMPF (Bit 0)                                          */
#define TIMER_SR_CMPF_Msk                 (0x1UL)                   /*!< CMPF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  CFGR  ========================================================== */
#define SPI_CFGR_FRAMESZ_Pos              (0UL)                     /*!< FRAMESZ (Bit 0)                                       */
#define SPI_CFGR_FRAMESZ_Msk              (0x1FUL)                  /*!< FRAMESZ (Bitfield-Mask: 0x1F)                         */
#define SPI_CFGR_SPIEN_Pos                (7UL)                     /*!< SPIEN (Bit 7)                                         */
#define SPI_CFGR_SPIEN_Msk                (0x80UL)                  /*!< SPIEN (Bitfield-Mask: 0x01)                           */
#define SPI_CFGR_TMSBF_Pos                (8UL)                     /*!< TMSBF (Bit 8)                                         */
#define SPI_CFGR_TMSBF_Msk                (0x100UL)                 /*!< TMSBF (Bitfield-Mask: 0x01)                           */
#define SPI_CFGR_RMSBF_Pos                (9UL)                     /*!< RMSBF (Bit 9)                                         */
#define SPI_CFGR_RMSBF_Msk                (0x200UL)                 /*!< RMSBF (Bitfield-Mask: 0x01)                           */
#define SPI_CFGR_CPOL_Pos                 (10UL)                    /*!< CPOL (Bit 10)                                         */
#define SPI_CFGR_CPOL_Msk                 (0x400UL)                 /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define SPI_CFGR_CPHA_Pos                 (11UL)                    /*!< CPHA (Bit 11)                                         */
#define SPI_CFGR_CPHA_Msk                 (0x800UL)                 /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define SPI_CFGR_TDMAEN_Pos               (12UL)                    /*!< TDMAEN (Bit 12)                                       */
#define SPI_CFGR_TDMAEN_Msk               (0x1000UL)                /*!< TDMAEN (Bitfield-Mask: 0x01)                          */
#define SPI_CFGR_RDMAEN_Pos               (13UL)                    /*!< RDMAEN (Bit 13)                                       */
#define SPI_CFGR_RDMAEN_Msk               (0x2000UL)                /*!< RDMAEN (Bitfield-Mask: 0x01)                          */
#define SPI_CFGR_MASTER_Pos               (15UL)                    /*!< MASTER (Bit 15)                                       */
#define SPI_CFGR_MASTER_Msk               (0x8000UL)                /*!< MASTER (Bitfield-Mask: 0x01)                          */
#define SPI_CFGR_CSPOL_Pos                (16UL)                    /*!< CSPOL (Bit 16)                                        */
#define SPI_CFGR_CSPOL_Msk                (0x10000UL)               /*!< CSPOL (Bitfield-Mask: 0x01)                           */
#define SPI_CFGR_PINCFG_Pos               (24UL)                    /*!< PINCFG (Bit 24)                                       */
#define SPI_CFGR_PINCFG_Msk               (0x1000000UL)             /*!< PINCFG (Bitfield-Mask: 0x01)                          */
/* ========================================================  CSCFGR  ========================================================= */
#define SPI_CSCFGR_CSSETUP_Pos            (0UL)                     /*!< CSSETUP (Bit 0)                                       */
#define SPI_CSCFGR_CSSETUP_Msk            (0xffUL)                  /*!< CSSETUP (Bitfield-Mask: 0xff)                         */
#define SPI_CSCFGR_CSHOLD_Pos             (8UL)                     /*!< CSHOLD (Bit 8)                                        */
#define SPI_CSCFGR_CSHOLD_Msk             (0xff00UL)                /*!< CSHOLD (Bitfield-Mask: 0xff)                          */
#define SPI_CSCFGR_CSIDLE_Pos             (16UL)                    /*!< CSIDLE (Bit 16)                                       */
#define SPI_CSCFGR_CSIDLE_Msk             (0xff0000UL)              /*!< CSIDLE (Bitfield-Mask: 0xff)                          */
/* ==========================================================  CR  =========================================================== */
#define SPI_CR_CONTEN_Pos                 (0UL)                     /*!< CONTEN (Bit 0)                                        */
#define SPI_CR_CONTEN_Msk                 (0x1UL)                   /*!< CONTEN (Bitfield-Mask: 0x01)                          */
#define SPI_CR_CSLOOSE_Pos                (1UL)                     /*!< CSLOOSE (Bit 1)                                       */
#define SPI_CR_CSLOOSE_Msk                (0x2UL)                   /*!< CSLOOSE (Bitfield-Mask: 0x01)                         */
#define SPI_CR_SPLDLY_Pos                 (14UL)                    /*!< SPLDLY (Bit 14)                                       */
#define SPI_CR_SPLDLY_Msk                 (0xc000UL)                /*!< SPLDLY (Bitfield-Mask: 0x03)                          */
#define SPI_CR_SCKL_Pos                   (16UL)                    /*!< SCKL (Bit 16)                                         */
#define SPI_CR_SCKL_Msk                   (0xff0000UL)              /*!< SCKL (Bitfield-Mask: 0xff)                            */
#define SPI_CR_SCKH_Pos                   (24UL)                    /*!< SCKH (Bit 24)                                         */
#define SPI_CR_SCKH_Msk                   (0xff000000UL)            /*!< SCKH (Bitfield-Mask: 0xff)                            */
/* ==========================================================  IER  ========================================================== */
#define SPI_IER_TNFIE_Pos                 (0UL)                     /*!< TNFIE (Bit 0)                                         */
#define SPI_IER_TNFIE_Msk                 (0x1UL)                   /*!< TNFIE (Bitfield-Mask: 0x01)                           */
#define SPI_IER_TUIE_Pos                  (1UL)                     /*!< TUIE (Bit 1)                                          */
#define SPI_IER_TUIE_Msk                  (0x2UL)                   /*!< TUIE (Bitfield-Mask: 0x01)                            */
#define SPI_IER_RNEIE_Pos                 (2UL)                     /*!< RNEIE (Bit 2)                                         */
#define SPI_IER_RNEIE_Msk                 (0x4UL)                   /*!< RNEIE (Bitfield-Mask: 0x01)                           */
#define SPI_IER_ROIE_Pos                  (3UL)                     /*!< ROIE (Bit 3)                                          */
#define SPI_IER_ROIE_Msk                  (0x8UL)                   /*!< ROIE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  SR  =========================================================== */
#define SPI_SR_TNFF_Pos                   (0UL)                     /*!< TNFF (Bit 0)                                          */
#define SPI_SR_TNFF_Msk                   (0x1UL)                   /*!< TNFF (Bitfield-Mask: 0x01)                            */
#define SPI_SR_TUFF_Pos                   (1UL)                     /*!< TUFF (Bit 1)                                          */
#define SPI_SR_TUFF_Msk                   (0x2UL)                   /*!< TUFF (Bitfield-Mask: 0x01)                            */
#define SPI_SR_RNEF_Pos                   (2UL)                     /*!< RNEF (Bit 2)                                          */
#define SPI_SR_RNEF_Msk                   (0x4UL)                   /*!< RNEF (Bitfield-Mask: 0x01)                            */
#define SPI_SR_ROFF_Pos                   (3UL)                     /*!< ROFF (Bit 3)                                          */
#define SPI_SR_ROFF_Msk                   (0x8UL)                   /*!< ROFF (Bitfield-Mask: 0x01)                            */
#define SPI_SR_MBF_Pos                    (7UL)                     /*!< MBF (Bit 7)                                           */
#define SPI_SR_MBF_Msk                    (0x80UL)                  /*!< MBF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  DR  =========================================================== */
#define SPI_DR_DATA_Pos                   (0UL)                     /*!< DATA (Bit 0)                                          */
#define SPI_DR_DATA_Msk                   (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */

/* =========================================================================================================================== */
/* ================                                           CMP                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  C0  =========================================================== */
#define CMP_C0_HYSTSEL_Pos                (0UL)                     /*!< HYSTSEL (Bit 0)                                       */
#define CMP_C0_HYSTSEL_Msk                (0x3UL)                   /*!< HYSTSEL (Bitfield-Mask: 0x03)                         */
#define CMP_C0_CMPEN_Pos                  (8UL)                     /*!< CMPEN (Bit 8)                                         */
#define CMP_C0_CMPEN_Msk                  (0x100UL)                 /*!< CMPEN (Bitfield-Mask: 0x01)                           */
#define CMP_C0_CMPOUTPINEN_Pos            (9UL)                     /*!< CMPOUTPINEN (Bit 9)                                   */
#define CMP_C0_CMPOUTPINEN_Msk            (0x200UL)                 /*!< CMPOUTPINEN (Bitfield-Mask: 0x01)                     */
#define CMP_C0_COS_Pos                    (10UL)                    /*!< COS (Bit 10)                                          */
#define CMP_C0_COS_Msk                    (0x400UL)                 /*!< COS (Bitfield-Mask: 0x01)                             */
#define CMP_C0_INV_Pos                    (11UL)                    /*!< INV (Bit 11)                                          */
#define CMP_C0_INV_Msk                    (0x800UL)                 /*!< INV (Bitfield-Mask: 0x01)                             */
#define CMP_C0_POE_Pos                    (13UL)                    /*!< POE (Bit 13)                                          */
#define CMP_C0_POE_Msk                    (0x2000UL)                /*!< POE (Bitfield-Mask: 0x01)                             */
#define CMP_C0_WINE_Pos                   (14UL)                    /*!< WINE (Bit 14)                                         */
#define CMP_C0_WINE_Msk                   (0x4000UL)                /*!< WINE (Bitfield-Mask: 0x01)                            */
#define CMP_C0_FILTEREN_Pos               (15UL)                    /*!< FILTEREN (Bit 15)                                     */
#define CMP_C0_FILTEREN_Msk               (0x8000UL)                /*!< FILTEREN (Bitfield-Mask: 0x01)                        */
#define CMP_C0_EDGETYPE_Pos               (16UL)                    /*!< EDGETYPE (Bit 16)                                     */
#define CMP_C0_EDGETYPE_Msk               (0x30000UL)               /*!< EDGETYPE (Bitfield-Mask: 0x03)                        */
#define CMP_C0_IE_Pos                     (18UL)                    /*!< IE (Bit 18)                                           */
#define CMP_C0_IE_Msk                     (0x40000UL)               /*!< IE (Bitfield-Mask: 0x01)                              */
/* ==========================================================  C1  =========================================================== */
#define CMP_C1_MODE_Pos                   (0UL)                     /*!< MODE (Bit 0)                                          */
#define CMP_C1_MODE_Msk                   (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
#define CMP_C1_INNSEL_Pos                 (4UL)                     /*!< INNSEL (Bit 4)                                        */
#define CMP_C1_INNSEL_Msk                 (0xf0UL)                  /*!< INNSEL (Bitfield-Mask: 0x0f)                          */
#define CMP_C1_INPSEL_Pos                 (12UL)                    /*!< INPSEL (Bit 12)                                       */
#define CMP_C1_INPSEL_Msk                 (0xf000UL)                /*!< INPSEL (Bitfield-Mask: 0x0f)                          */
#define CMP_C1_LPCHN0_Pos                 (16UL)                    /*!< LPCHN0 (Bit 16)                                       */
#define CMP_C1_LPCHN0_Msk                 (0x10000UL)               /*!< LPCHN0 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN1_Pos                 (17UL)                    /*!< LPCHN1 (Bit 17)                                       */
#define CMP_C1_LPCHN1_Msk                 (0x20000UL)               /*!< LPCHN1 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN2_Pos                 (18UL)                    /*!< LPCHN2 (Bit 18)                                       */
#define CMP_C1_LPCHN2_Msk                 (0x40000UL)               /*!< LPCHN2 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN3_Pos                 (19UL)                    /*!< LPCHN3 (Bit 19)                                       */
#define CMP_C1_LPCHN3_Msk                 (0x80000UL)               /*!< LPCHN3 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN4_Pos                 (20UL)                    /*!< LPCHN4 (Bit 20)                                       */
#define CMP_C1_LPCHN4_Msk                 (0x100000UL)              /*!< LPCHN4 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN5_Pos                 (21UL)                    /*!< LPCHN5 (Bit 21)                                       */
#define CMP_C1_LPCHN5_Msk                 (0x200000UL)              /*!< LPCHN5 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN6_Pos                 (22UL)                    /*!< LPCHN6 (Bit 22)                                       */
#define CMP_C1_LPCHN6_Msk                 (0x400000UL)              /*!< LPCHN6 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPCHN7_Pos                 (23UL)                    /*!< LPCHN7 (Bit 23)                                       */
#define CMP_C1_LPCHN7_Msk                 (0x800000UL)              /*!< LPCHN7 (Bitfield-Mask: 0x01)                          */
#define CMP_C1_LPDAC_Pos                  (24UL)                    /*!< LPDAC (Bit 24)                                        */
#define CMP_C1_LPDAC_Msk                  (0x1000000UL)             /*!< LPDAC (Bitfield-Mask: 0x01)                           */
/* ==========================================================  C2  =========================================================== */
#define CMP_C2_LMSCNT_Pos                 (0UL)                     /*!< LMSCNT (Bit 0)                                        */
#define CMP_C2_LMSCNT_Msk                 (0xffffUL)                /*!< LMSCNT (Bitfield-Mask: 0xffff)                        */
#define CMP_C2_STABTIME_Pos               (24UL)                    /*!< STABTIME (Bit 24)                                     */
#define CMP_C2_STABTIME_Msk               (0xff000000UL)            /*!< STABTIME (Bitfield-Mask: 0xff)                        */
/* ==========================================================  C3  =========================================================== */
#define CMP_C3_LMPRE0_Pos                 (0UL)                     /*!< LMPRE0 (Bit 0)                                        */
#define CMP_C3_LMPRE0_Msk                 (0x1UL)                   /*!< LMPRE0 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE1_Pos                 (1UL)                     /*!< LMPRE1 (Bit 1)                                        */
#define CMP_C3_LMPRE1_Msk                 (0x2UL)                   /*!< LMPRE1 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE2_Pos                 (2UL)                     /*!< LMPRE2 (Bit 2)                                        */
#define CMP_C3_LMPRE2_Msk                 (0x4UL)                   /*!< LMPRE2 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE3_Pos                 (3UL)                     /*!< LMPRE3 (Bit 3)                                        */
#define CMP_C3_LMPRE3_Msk                 (0x8UL)                   /*!< LMPRE3 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE4_Pos                 (4UL)                     /*!< LMPRE4 (Bit 4)                                        */
#define CMP_C3_LMPRE4_Msk                 (0x10UL)                  /*!< LMPRE4 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE5_Pos                 (5UL)                     /*!< LMPRE5 (Bit 5)                                        */
#define CMP_C3_LMPRE5_Msk                 (0x20UL)                  /*!< LMPRE5 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE6_Pos                 (6UL)                     /*!< LMPRE6 (Bit 6)                                        */
#define CMP_C3_LMPRE6_Msk                 (0x40UL)                  /*!< LMPRE6 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE7_Pos                 (7UL)                     /*!< LMPRE7 (Bit 7)                                        */
#define CMP_C3_LMPRE7_Msk                 (0x80UL)                  /*!< LMPRE7 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_LMPRE8_Pos                 (8UL)                     /*!< LMPRE8 (Bit 8)                                        */
#define CMP_C3_LMPRE8_Msk                 (0x100UL)                 /*!< LMPRE8 (Bitfield-Mask: 0x01)                          */
#define CMP_C3_NMPRE_Pos                  (9UL)                     /*!< NMPRE (Bit 9)                                         */
#define CMP_C3_NMPRE_Msk                  (0x200UL)                 /*!< NMPRE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  C4  =========================================================== */
#define CMP_C4_DACVAL_Pos                 (0UL)                     /*!< DACVAL (Bit 0)                                        */
#define CMP_C4_DACVAL_Msk                 (0xffUL)                  /*!< DACVAL (Bitfield-Mask: 0xff)                          */
#define CMP_C4_DACEN_Pos                  (8UL)                     /*!< DACEN (Bit 8)                                         */
#define CMP_C4_DACEN_Msk                  (0x100UL)                 /*!< DACEN (Bitfield-Mask: 0x01)                           */
#define CMP_C4_DACREF_Pos                 (9UL)                     /*!< DACREF (Bit 9)                                        */
#define CMP_C4_DACREF_Msk                 (0x200UL)                 /*!< DACREF (Bitfield-Mask: 0x01)                          */
#define CMP_C4_DACPINEN_Pos               (10UL)                    /*!< DACPINEN (Bit 10)                                     */
#define CMP_C4_DACPINEN_Msk               (0x400UL)                 /*!< DACPINEN (Bitfield-Mask: 0x01)                        */
/* ==========================================================  C5  =========================================================== */
#define CMP_C5_POAS_Pos                   (0UL)                     /*!< POAS (Bit 0)                                          */
#define CMP_C5_POAS_Msk                   (0xfUL)                   /*!< POAS (Bitfield-Mask: 0x0f)                            */
#define CMP_C5_POBS_Pos                   (4UL)                     /*!< POBS (Bit 4)                                          */
#define CMP_C5_POBS_Msk                   (0xf0UL)                  /*!< POBS (Bitfield-Mask: 0x0f)                            */
#define CMP_C5_POCS_Pos                   (8UL)                     /*!< POCS (Bit 8)                                          */
#define CMP_C5_POCS_Msk                   (0xf00UL)                 /*!< POCS (Bitfield-Mask: 0x0f)                            */
#define CMP_C5_PODS_Pos                   (12UL)                    /*!< PODS (Bit 12)                                         */
#define CMP_C5_PODS_Msk                   (0xf000UL)                /*!< PODS (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  C6  =========================================================== */
#define CMP_C6_FILTERWIDTH_Pos            (0UL)                     /*!< FILTERWIDTH (Bit 0)                                   */
#define CMP_C6_FILTERWIDTH_Msk            (0xffUL)                  /*!< FILTERWIDTH (Bitfield-Mask: 0xff)                     */
#define CMP_C6_FILTERDIV_Pos              (16UL)                    /*!< FILTERDIV (Bit 16)                                    */
#define CMP_C6_FILTERDIV_Msk              (0x3ff0000UL)             /*!< FILTERDIV (Bitfield-Mask: 0x3ff)                      */
/* ==========================================================  DR  =========================================================== */
#define CMP_DR_LMCO0_Pos                  (0UL)                     /*!< LMCO0 (Bit 0)                                         */
#define CMP_DR_LMCO0_Msk                  (0x1UL)                   /*!< LMCO0 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO1_Pos                  (1UL)                     /*!< LMCO1 (Bit 1)                                         */
#define CMP_DR_LMCO1_Msk                  (0x2UL)                   /*!< LMCO1 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO2_Pos                  (2UL)                     /*!< LMCO2 (Bit 2)                                         */
#define CMP_DR_LMCO2_Msk                  (0x4UL)                   /*!< LMCO2 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO3_Pos                  (3UL)                     /*!< LMCO3 (Bit 3)                                         */
#define CMP_DR_LMCO3_Msk                  (0x8UL)                   /*!< LMCO3 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO4_Pos                  (4UL)                     /*!< LMCO4 (Bit 4)                                         */
#define CMP_DR_LMCO4_Msk                  (0x10UL)                  /*!< LMCO4 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO5_Pos                  (5UL)                     /*!< LMCO5 (Bit 5)                                         */
#define CMP_DR_LMCO5_Msk                  (0x20UL)                  /*!< LMCO5 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO6_Pos                  (6UL)                     /*!< LMCO6 (Bit 6)                                         */
#define CMP_DR_LMCO6_Msk                  (0x40UL)                  /*!< LMCO6 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO7_Pos                  (7UL)                     /*!< LMCO7 (Bit 7)                                         */
#define CMP_DR_LMCO7_Msk                  (0x80UL)                  /*!< LMCO7 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_LMCO8_Pos                  (8UL)                     /*!< LMCO8 (Bit 8)                                         */
#define CMP_DR_LMCO8_Msk                  (0x100UL)                 /*!< LMCO8 (Bitfield-Mask: 0x01)                           */
#define CMP_DR_NMCO_Pos                   (9UL)                     /*!< NMCO (Bit 9)                                          */
#define CMP_DR_NMCO_Msk                   (0x200UL)                 /*!< NMCO (Bitfield-Mask: 0x01)                            */
/* ==========================================================  SR  =========================================================== */
#define CMP_SR_LMCHF0_Pos                 (0UL)                     /*!< LMCHF0 (Bit 0)                                        */
#define CMP_SR_LMCHF0_Msk                 (0x1UL)                   /*!< LMCHF0 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF1_Pos                 (1UL)                     /*!< LMCHF1 (Bit 1)                                        */
#define CMP_SR_LMCHF1_Msk                 (0x2UL)                   /*!< LMCHF1 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF2_Pos                 (2UL)                     /*!< LMCHF2 (Bit 2)                                        */
#define CMP_SR_LMCHF2_Msk                 (0x4UL)                   /*!< LMCHF2 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF3_Pos                 (3UL)                     /*!< LMCHF3 (Bit 3)                                        */
#define CMP_SR_LMCHF3_Msk                 (0x8UL)                   /*!< LMCHF3 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF4_Pos                 (4UL)                     /*!< LMCHF4 (Bit 4)                                        */
#define CMP_SR_LMCHF4_Msk                 (0x10UL)                  /*!< LMCHF4 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF5_Pos                 (5UL)                     /*!< LMCHF5 (Bit 5)                                        */
#define CMP_SR_LMCHF5_Msk                 (0x20UL)                  /*!< LMCHF5 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF6_Pos                 (6UL)                     /*!< LMCHF6 (Bit 6)                                        */
#define CMP_SR_LMCHF6_Msk                 (0x40UL)                  /*!< LMCHF6 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF7_Pos                 (7UL)                     /*!< LMCHF7 (Bit 7)                                        */
#define CMP_SR_LMCHF7_Msk                 (0x80UL)                  /*!< LMCHF7 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_LMCHF8_Pos                 (8UL)                     /*!< LMCHF8 (Bit 8)                                        */
#define CMP_SR_LMCHF8_Msk                 (0x100UL)                 /*!< LMCHF8 (Bitfield-Mask: 0x01)                          */
#define CMP_SR_NMCHF_Pos                  (9UL)                     /*!< NMCHF (Bit 9)                                         */
#define CMP_SR_NMCHF_Msk                  (0x200UL)                 /*!< NMCHF (Bitfield-Mask: 0x01)                           */
#define CMP_SR_READY_Pos                  (16UL)                    /*!< READY (Bit 16)                                        */
#define CMP_SR_READY_Msk                  (0x10000UL)               /*!< READY (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                            PMC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define PMC_CR_LVDEN_Pos                  (0UL)                     /*!< LVDEN (Bit 0)                                         */
#define PMC_CR_LVDEN_Msk                  (0x1UL)                   /*!< LVDEN (Bitfield-Mask: 0x01)                           */
#define PMC_CR_LVDLEVEL_Pos               (1UL)                     /*!< LVDLEVEL (Bit 1)                                      */
#define PMC_CR_LVDLEVEL_Msk               (0x2UL)                   /*!< LVDLEVEL (Bitfield-Mask: 0x01)                        */
#define PMC_CR_LVDIE_Pos                  (2UL)                     /*!< LVDIE (Bit 2)                                         */
#define PMC_CR_LVDIE_Msk                  (0x4UL)                   /*!< LVDIE (Bitfield-Mask: 0x01)                           */
#define PMC_CR_LVREN_Pos                  (3UL)                     /*!< LVREN (Bit 3)                                         */
#define PMC_CR_LVREN_Msk                  (0x8UL)                   /*!< LVREN (Bitfield-Mask: 0x01)                           */
#define PMC_CR_POWERMODE_Pos              (4UL)                     /*!< POWERMODE (Bit 4)                                     */
#define PMC_CR_POWERMODE_Msk              (0x30UL)                  /*!< POWERMODE (Bitfield-Mask: 0x03)                       */
#define PMC_CR_NMIIE_Pos                  (6UL)                     /*!< NMIIE (Bit 6)                                         */
#define PMC_CR_NMIIE_Msk                  (0x40UL)                  /*!< NMIIE (Bitfield-Mask: 0x01)                           */
#define PMC_CR_LVDF_Pos                   (7UL)                     /*!< LVDF (Bit 7)                                          */
#define PMC_CR_LVDF_Msk                   (0x80UL)                  /*!< LVDF (Bitfield-Mask: 0x01)                            */
#define PMC_CR_WKUPF_Pos                  (8UL)                     /*!< WKUPF (Bit 8)                                         */
#define PMC_CR_WKUPF_Msk                  (0x100UL)                 /*!< WKUPF (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PWE  ========================================================== */
#define PMC_PWE_CMP0_WE_Pos               (0UL)                     /*!< CMP0_WE (Bit 0)                                       */
#define PMC_PWE_CMP0_WE_Msk               (0x1UL)                   /*!< CMP0_WE (Bitfield-Mask: 0x01)                         */
#define PMC_PWE_TIMER0_WE_Pos             (3UL)                     /*!< TIMER0_WE (Bit 3)                                     */
#define PMC_PWE_TIMER0_WE_Msk             (0x8UL)                   /*!< TIMER0_WE (Bitfield-Mask: 0x01)                       */
#define PMC_PWE_TIMER1_WE_Pos             (4UL)                     /*!< TIMER1_WE (Bit 4)                                     */
#define PMC_PWE_TIMER1_WE_Msk             (0x10UL)                  /*!< TIMER1_WE (Bitfield-Mask: 0x01)                       */
#define PMC_PWE_TIMER2_WE_Pos             (5UL)                     /*!< TIMER2_WE (Bit 5)                                     */
#define PMC_PWE_TIMER2_WE_Msk             (0x20UL)                  /*!< TIMER2_WE (Bitfield-Mask: 0x01)                       */
#define PMC_PWE_TIMER3_WE_Pos             (6UL)                     /*!< TIMER3_WE (Bit 6)                                     */
#define PMC_PWE_TIMER3_WE_Msk             (0x40UL)                  /*!< TIMER3_WE (Bitfield-Mask: 0x01)                       */
#define PMC_PWE_RTC_WE_Pos                (8UL)                     /*!< RTC_WE (Bit 8)                                        */
#define PMC_PWE_RTC_WE_Msk                (0x100UL)                 /*!< RTC_WE (Bitfield-Mask: 0x01)                          */
#define PMC_PWE_LVD_WE_Pos                (9UL)                     /*!< LVD_WE (Bit 9)                                        */
#define PMC_PWE_LVD_WE_Msk                (0x200UL)                 /*!< LVD_WE (Bitfield-Mask: 0x01)                          */
#define PMC_PWE_NMI_WE_Pos                (10UL)                    /*!< NMI_WE (Bit 10)                                       */
#define PMC_PWE_NMI_WE_Msk                (0x400UL)                 /*!< NMI_WE (Bitfield-Mask: 0x01)                          */
#define PMC_PWE_GPIO_WE_Pos               (11UL)                    /*!< GPIO_WE (Bit 11)                                      */
#define PMC_PWE_GPIO_WE_Msk               (0x800UL)                 /*!< GPIO_WE (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ODR  ========================================================== */
#define GPIO_ODR_ODR0_Pos                 (0UL)                     /*!< ODR0 (Bit 0)                                          */
#define GPIO_ODR_ODR0_Msk                 (0x1UL)                   /*!< ODR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR1_Pos                 (1UL)                     /*!< ODR1 (Bit 1)                                          */
#define GPIO_ODR_ODR1_Msk                 (0x2UL)                   /*!< ODR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR2_Pos                 (2UL)                     /*!< ODR2 (Bit 2)                                          */
#define GPIO_ODR_ODR2_Msk                 (0x4UL)                   /*!< ODR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR3_Pos                 (3UL)                     /*!< ODR3 (Bit 3)                                          */
#define GPIO_ODR_ODR3_Msk                 (0x8UL)                   /*!< ODR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR4_Pos                 (4UL)                     /*!< ODR4 (Bit 4)                                          */
#define GPIO_ODR_ODR4_Msk                 (0x10UL)                  /*!< ODR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR5_Pos                 (5UL)                     /*!< ODR5 (Bit 5)                                          */
#define GPIO_ODR_ODR5_Msk                 (0x20UL)                  /*!< ODR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR6_Pos                 (6UL)                     /*!< ODR6 (Bit 6)                                          */
#define GPIO_ODR_ODR6_Msk                 (0x40UL)                  /*!< ODR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR7_Pos                 (7UL)                     /*!< ODR7 (Bit 7)                                          */
#define GPIO_ODR_ODR7_Msk                 (0x80UL)                  /*!< ODR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR8_Pos                 (8UL)                     /*!< ODR8 (Bit 8)                                          */
#define GPIO_ODR_ODR8_Msk                 (0x100UL)                 /*!< ODR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR9_Pos                 (9UL)                     /*!< ODR9 (Bit 9)                                          */
#define GPIO_ODR_ODR9_Msk                 (0x200UL)                 /*!< ODR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR10_Pos                (10UL)                    /*!< ODR10 (Bit 10)                                        */
#define GPIO_ODR_ODR10_Msk                (0x400UL)                 /*!< ODR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR11_Pos                (11UL)                    /*!< ODR11 (Bit 11)                                        */
#define GPIO_ODR_ODR11_Msk                (0x800UL)                 /*!< ODR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR12_Pos                (12UL)                    /*!< ODR12 (Bit 12)                                        */
#define GPIO_ODR_ODR12_Msk                (0x1000UL)                /*!< ODR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR13_Pos                (13UL)                    /*!< ODR13 (Bit 13)                                        */
#define GPIO_ODR_ODR13_Msk                (0x2000UL)                /*!< ODR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR14_Pos                (14UL)                    /*!< ODR14 (Bit 14)                                        */
#define GPIO_ODR_ODR14_Msk                (0x4000UL)                /*!< ODR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR15_Pos                (15UL)                    /*!< ODR15 (Bit 15)                                        */
#define GPIO_ODR_ODR15_Msk                (0x8000UL)                /*!< ODR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR16_Pos                (16UL)                    /*!< ODR16 (Bit 16)                                        */
#define GPIO_ODR_ODR16_Msk                (0x10000UL)               /*!< ODR16 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR17_Pos                (17UL)                    /*!< ODR17 (Bit 17)                                        */
#define GPIO_ODR_ODR17_Msk                (0x20000UL)               /*!< ODR17 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR18_Pos                (18UL)                    /*!< ODR18 (Bit 18)                                        */
#define GPIO_ODR_ODR18_Msk                (0x40000UL)               /*!< ODR18 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR19_Pos                (19UL)                    /*!< ODR19 (Bit 19)                                        */
#define GPIO_ODR_ODR19_Msk                (0x80000UL)               /*!< ODR19 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR20_Pos                (20UL)                    /*!< ODR20 (Bit 20)                                        */
#define GPIO_ODR_ODR20_Msk                (0x100000UL)              /*!< ODR20 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR21_Pos                (21UL)                    /*!< ODR21 (Bit 21)                                        */
#define GPIO_ODR_ODR21_Msk                (0x200000UL)              /*!< ODR21 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR22_Pos                (22UL)                    /*!< ODR22 (Bit 22)                                        */
#define GPIO_ODR_ODR22_Msk                (0x400000UL)              /*!< ODR22 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR23_Pos                (23UL)                    /*!< ODR23 (Bit 23)                                        */
#define GPIO_ODR_ODR23_Msk                (0x800000UL)              /*!< ODR23 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR24_Pos                (24UL)                    /*!< ODR24 (Bit 24)                                        */
#define GPIO_ODR_ODR24_Msk                (0x1000000UL)             /*!< ODR24 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR25_Pos                (25UL)                    /*!< ODR25 (Bit 25)                                        */
#define GPIO_ODR_ODR25_Msk                (0x2000000UL)             /*!< ODR25 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR26_Pos                (26UL)                    /*!< ODR26 (Bit 26)                                        */
#define GPIO_ODR_ODR26_Msk                (0x4000000UL)             /*!< ODR26 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR27_Pos                (27UL)                    /*!< ODR27 (Bit 27)                                        */
#define GPIO_ODR_ODR27_Msk                (0x8000000UL)             /*!< ODR27 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR28_Pos                (28UL)                    /*!< ODR28 (Bit 28)                                        */
#define GPIO_ODR_ODR28_Msk                (0x10000000UL)            /*!< ODR28 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR29_Pos                (29UL)                    /*!< ODR29 (Bit 29)                                        */
#define GPIO_ODR_ODR29_Msk                (0x20000000UL)            /*!< ODR29 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR30_Pos                (30UL)                    /*!< ODR30 (Bit 30)                                        */
#define GPIO_ODR_ODR30_Msk                (0x40000000UL)            /*!< ODR30 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR31_Pos                (31UL)                    /*!< ODR31 (Bit 31)                                        */
#define GPIO_ODR_ODR31_Msk                (0x80000000UL)            /*!< ODR31 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  OSR  ========================================================== */
#define GPIO_OSR_OSR0_Pos                 (0UL)                     /*!< OSR0 (Bit 0)                                          */
#define GPIO_OSR_OSR0_Msk                 (0x1UL)                   /*!< OSR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR1_Pos                 (1UL)                     /*!< OSR1 (Bit 1)                                          */
#define GPIO_OSR_OSR1_Msk                 (0x2UL)                   /*!< OSR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR2_Pos                 (2UL)                     /*!< OSR2 (Bit 2)                                          */
#define GPIO_OSR_OSR2_Msk                 (0x4UL)                   /*!< OSR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR3_Pos                 (3UL)                     /*!< OSR3 (Bit 3)                                          */
#define GPIO_OSR_OSR3_Msk                 (0x8UL)                   /*!< OSR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR4_Pos                 (4UL)                     /*!< OSR4 (Bit 4)                                          */
#define GPIO_OSR_OSR4_Msk                 (0x10UL)                  /*!< OSR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR5_Pos                 (5UL)                     /*!< OSR5 (Bit 5)                                          */
#define GPIO_OSR_OSR5_Msk                 (0x20UL)                  /*!< OSR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR6_Pos                 (6UL)                     /*!< OSR6 (Bit 6)                                          */
#define GPIO_OSR_OSR6_Msk                 (0x40UL)                  /*!< OSR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR7_Pos                 (7UL)                     /*!< OSR7 (Bit 7)                                          */
#define GPIO_OSR_OSR7_Msk                 (0x80UL)                  /*!< OSR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR8_Pos                 (8UL)                     /*!< OSR8 (Bit 8)                                          */
#define GPIO_OSR_OSR8_Msk                 (0x100UL)                 /*!< OSR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR9_Pos                 (9UL)                     /*!< OSR9 (Bit 9)                                          */
#define GPIO_OSR_OSR9_Msk                 (0x200UL)                 /*!< OSR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_OSR_OSR10_Pos                (10UL)                    /*!< OSR10 (Bit 10)                                        */
#define GPIO_OSR_OSR10_Msk                (0x400UL)                 /*!< OSR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR11_Pos                (11UL)                    /*!< OSR11 (Bit 11)                                        */
#define GPIO_OSR_OSR11_Msk                (0x800UL)                 /*!< OSR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR12_Pos                (12UL)                    /*!< OSR12 (Bit 12)                                        */
#define GPIO_OSR_OSR12_Msk                (0x1000UL)                /*!< OSR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR13_Pos                (13UL)                    /*!< OSR13 (Bit 13)                                        */
#define GPIO_OSR_OSR13_Msk                (0x2000UL)                /*!< OSR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR14_Pos                (14UL)                    /*!< OSR14 (Bit 14)                                        */
#define GPIO_OSR_OSR14_Msk                (0x4000UL)                /*!< OSR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR15_Pos                (15UL)                    /*!< OSR15 (Bit 15)                                        */
#define GPIO_OSR_OSR15_Msk                (0x8000UL)                /*!< OSR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR16_Pos                 (16UL)                    /*!< OSR16 (Bit 16)                                        */
#define GPIO_OSR_OSR16_Msk                (0x10000UL)               /*!< OSR16 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR17_Pos                (17UL)                    /*!< OSR17 (Bit 17)                                        */
#define GPIO_OSR_OSR17_Msk                (0x20000UL)               /*!< OSR17 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR18_Pos                (18UL)                    /*!< OSR18 (Bit 18)                                        */
#define GPIO_OSR_OSR18_Msk                (0x40000UL)               /*!< OSR18 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR19_Pos                (19UL)                    /*!< OSR19 (Bit 19)                                        */
#define GPIO_OSR_OSR19_Msk                (0x80000UL)               /*!< OSR19 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR20_Pos                (20UL)                    /*!< OSR20 (Bit 20)                                        */
#define GPIO_OSR_OSR20_Msk                (0x100000UL)              /*!< OSR20 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR21_Pos                (21UL)                    /*!< OSR21 (Bit 21)                                        */
#define GPIO_OSR_OSR21_Msk                (0x200000UL)              /*!< OSR21 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR22_Pos                (22UL)                    /*!< OSR22 (Bit 22)                                        */
#define GPIO_OSR_OSR22_Msk                (0x400000UL)              /*!< OSR22 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR23_Pos                (23UL)                    /*!< OSR23 (Bit 23)                                        */
#define GPIO_OSR_OSR23_Msk                (0x800000UL)              /*!< OSR23 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR24_Pos                (24UL)                    /*!< OSR24 (Bit 24)                                        */
#define GPIO_OSR_OSR24_Msk                (0x1000000UL)             /*!< OSR24 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR25_Pos                (25UL)                    /*!< OSR25 (Bit 25)                                        */
#define GPIO_OSR_OSR25_Msk                (0x2000000UL)             /*!< OSR25 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR26_Pos                (26UL)                    /*!< OSR26 (Bit 26)                                        */
#define GPIO_OSR_OSR26_Msk                (0x4000000UL)             /*!< OSR26 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR27_Pos                (27UL)                    /*!< OSR27 (Bit 27)                                        */
#define GPIO_OSR_OSR27_Msk                (0x8000000UL)             /*!< OSR27 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR28_Pos                (28UL)                    /*!< OSR28 (Bit 28)                                        */
#define GPIO_OSR_OSR28_Msk                (0x10000000UL)            /*!< OSR28 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR29_Pos                (29UL)                    /*!< OSR29 (Bit 29)                                        */
#define GPIO_OSR_OSR29_Msk                (0x20000000UL)            /*!< OSR29 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR30_Pos                (30UL)                    /*!< OSR30 (Bit 30)                                        */
#define GPIO_OSR_OSR30_Msk                (0x40000000UL)            /*!< OSR30 (Bitfield-Mask: 0x01)                           */
#define GPIO_OSR_OSR31_Pos                (31UL)                    /*!< OSR31 (Bit 31)                                        */
#define GPIO_OSR_OSR31_Msk                (0x80000000UL)            /*!< OSR31 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ORR  ========================================================== */
#define GPIO_ORR_ORR0_Pos                 (0UL)                     /*!< ORR0 (Bit 0)                                          */
#define GPIO_ORR_ORR0_Msk                 (0x1UL)                   /*!< ORR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR1_Pos                 (1UL)                     /*!< ORR1 (Bit 1)                                          */
#define GPIO_ORR_ORR1_Msk                 (0x2UL)                   /*!< ORR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR2_Pos                 (2UL)                     /*!< ORR2 (Bit 2)                                          */
#define GPIO_ORR_ORR2_Msk                 (0x4UL)                   /*!< ORR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR3_Pos                 (3UL)                     /*!< ORR3 (Bit 3)                                          */
#define GPIO_ORR_ORR3_Msk                 (0x8UL)                   /*!< ORR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR4_Pos                 (4UL)                     /*!< ORR4 (Bit 4)                                          */
#define GPIO_ORR_ORR4_Msk                 (0x10UL)                  /*!< ORR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR5_Pos                 (5UL)                     /*!< ORR5 (Bit 5)                                          */
#define GPIO_ORR_ORR5_Msk                 (0x20UL)                  /*!< ORR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR6_Pos                 (6UL)                     /*!< ORR6 (Bit 6)                                          */
#define GPIO_ORR_ORR6_Msk                 (0x40UL)                  /*!< ORR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR7_Pos                 (7UL)                     /*!< ORR7 (Bit 7)                                          */
#define GPIO_ORR_ORR7_Msk                 (0x80UL)                  /*!< ORR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR8_Pos                 (8UL)                     /*!< ORR8 (Bit 8)                                          */
#define GPIO_ORR_ORR8_Msk                 (0x100UL)                 /*!< ORR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR9_Pos                 (9UL)                     /*!< ORR9 (Bit 9)                                          */
#define GPIO_ORR_ORR9_Msk                 (0x200UL)                 /*!< ORR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_ORR_ORR10_Pos                (10UL)                    /*!< ORR10 (Bit 10)                                        */
#define GPIO_ORR_ORR10_Msk                (0x400UL)                 /*!< ORR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR11_Pos                (11UL)                    /*!< ORR11 (Bit 11)                                        */
#define GPIO_ORR_ORR11_Msk                (0x800UL)                 /*!< ORR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR12_Pos                (12UL)                    /*!< ORR12 (Bit 12)                                        */
#define GPIO_ORR_ORR12_Msk                (0x1000UL)                /*!< ORR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR13_Pos                (13UL)                    /*!< ORR13 (Bit 13)                                        */
#define GPIO_ORR_ORR13_Msk                (0x2000UL)                /*!< ORR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR14_Pos                (14UL)                    /*!< ORR14 (Bit 14)                                        */
#define GPIO_ORR_ORR14_Msk                (0x4000UL)                /*!< ORR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR15_Pos                (15UL)                    /*!< ORR15 (Bit 15)                                        */
#define GPIO_ORR_ORR15_Msk                (0x8000UL)                /*!< ORR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR16_Pos                (16UL)                    /*!< ORR16 (Bit 16)                                        */
#define GPIO_ORR_ORR16_Msk                (0x10000UL)               /*!< ORR16 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR17_Pos                (17UL)                    /*!< ORR17 (Bit 17)                                        */
#define GPIO_ORR_ORR17_Msk                (0x20000UL)               /*!< ORR17 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR18_Pos                (18UL)                    /*!< ORR18 (Bit 18)                                        */
#define GPIO_ORR_ORR18_Msk                (0x40000UL)               /*!< ORR18 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR19_Pos                (19UL)                    /*!< ORR19 (Bit 19)                                        */
#define GPIO_ORR_ORR19_Msk                (0x80000UL)               /*!< ORR19 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR20_Pos                (20UL)                    /*!< ORR20 (Bit 20)                                        */
#define GPIO_ORR_ORR20_Msk                (0x100000UL)              /*!< ORR20 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR21_Pos                (21UL)                    /*!< ORR21 (Bit 21)                                        */
#define GPIO_ORR_ORR21_Msk                (0x200000UL)              /*!< ORR21 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR22_Pos                (22UL)                    /*!< ORR22 (Bit 22)                                        */
#define GPIO_ORR_ORR22_Msk                (0x400000UL)              /*!< ORR22 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR23_Pos                (23UL)                    /*!< ORR23 (Bit 23)                                        */
#define GPIO_ORR_ORR23_Msk                (0x800000UL)              /*!< ORR23 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR24_Pos                (24UL)                    /*!< ORR24 (Bit 24)                                        */
#define GPIO_ORR_ORR24_Msk                (0x1000000UL)             /*!< ORR24 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR25_Pos                (25UL)                    /*!< ORR25 (Bit 25)                                        */
#define GPIO_ORR_ORR25_Msk                (0x2000000UL)             /*!< ORR25 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR26_Pos                (26UL)                    /*!< ORR26 (Bit 26)                                        */
#define GPIO_ORR_ORR26_Msk                (0x4000000UL)             /*!< ORR26 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR27_Pos                (27UL)                    /*!< ORR27 (Bit 27)                                        */
#define GPIO_ORR_ORR27_Msk                (0x8000000UL)             /*!< ORR27 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR29_Pos                (29UL)                    /*!< ORR29 (Bit 29)                                        */
#define GPIO_ORR_ORR29_Msk                (0x20000000UL)            /*!< ORR29 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR30_Pos                (30UL)                    /*!< ORR30 (Bit 30)                                        */
#define GPIO_ORR_ORR30_Msk                (0x40000000UL)            /*!< ORR30 (Bitfield-Mask: 0x01)                           */
#define GPIO_ORR_ORR31_Pos                (31UL)                    /*!< ORR31 (Bit 31)                                        */
#define GPIO_ORR_ORR31_Msk                (0x80000000UL)            /*!< ORR31 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  OTR  ========================================================== */
#define GPIO_OTR_OTR0_Pos                 (0UL)                     /*!< OTR0 (Bit 0)                                          */
#define GPIO_OTR_OTR0_Msk                 (0x1UL)                   /*!< OTR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR1_Pos                 (1UL)                     /*!< OTR1 (Bit 1)                                          */
#define GPIO_OTR_OTR1_Msk                 (0x2UL)                   /*!< OTR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR2_Pos                 (2UL)                     /*!< OTR2 (Bit 2)                                          */
#define GPIO_OTR_OTR2_Msk                 (0x4UL)                   /*!< OTR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR3_Pos                 (3UL)                     /*!< OTR3 (Bit 3)                                          */
#define GPIO_OTR_OTR3_Msk                 (0x8UL)                   /*!< OTR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR4_Pos                 (4UL)                     /*!< OTR4 (Bit 4)                                          */
#define GPIO_OTR_OTR4_Msk                 (0x10UL)                  /*!< OTR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR5_Pos                 (5UL)                     /*!< OTR5 (Bit 5)                                          */
#define GPIO_OTR_OTR5_Msk                 (0x20UL)                  /*!< OTR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR6_Pos                 (6UL)                     /*!< OTR6 (Bit 6)                                          */
#define GPIO_OTR_OTR6_Msk                 (0x40UL)                  /*!< OTR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR7_Pos                 (7UL)                     /*!< OTR7 (Bit 7)                                          */
#define GPIO_OTR_OTR7_Msk                 (0x80UL)                  /*!< OTR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR8_Pos                 (8UL)                     /*!< OTR8 (Bit 8)                                          */
#define GPIO_OTR_OTR8_Msk                 (0x100UL)                 /*!< OTR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR9_Pos                 (9UL)                     /*!< OTR9 (Bit 9)                                          */
#define GPIO_OTR_OTR9_Msk                 (0x200UL)                 /*!< OTR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_OTR_OTR10_Pos                (10UL)                    /*!< OTR10 (Bit 10)                                        */
#define GPIO_OTR_OTR10_Msk                (0x400UL)                 /*!< OTR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR11_Pos                (11UL)                    /*!< OTR11 (Bit 11)                                        */
#define GPIO_OTR_OTR11_Msk                (0x800UL)                 /*!< OTR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR12_Pos                (12UL)                    /*!< OTR12 (Bit 12)                                        */
#define GPIO_OTR_OTR12_Msk                (0x1000UL)                /*!< OTR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR13_Pos                (13UL)                    /*!< OTR13 (Bit 13)                                        */
#define GPIO_OTR_OTR13_Msk                (0x2000UL)                /*!< OTR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR14_Pos                (14UL)                    /*!< OTR14 (Bit 14)                                        */
#define GPIO_OTR_OTR14_Msk                (0x4000UL)                /*!< OTR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR15_Pos                (15UL)                    /*!< OTR15 (Bit 15)                                        */
#define GPIO_OTR_OTR15_Msk                (0x8000UL)                /*!< OTR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR16_Pos                (16UL)                    /*!< OTR16 (Bit 16)                                        */
#define GPIO_OTR_OTR16_Msk                (0x10000UL)               /*!< OTR16 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR17_Pos                (17UL)                    /*!< OTR17 (Bit 17)                                        */
#define GPIO_OTR_OTR17_Msk                (0x20000UL)               /*!< OTR17 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR18_Pos                (18UL)                    /*!< OTR18 (Bit 18)                                        */
#define GPIO_OTR_OTR18_Msk                (0x40000UL)               /*!< OTR18 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR19_Pos                (19UL)                    /*!< OTR19 (Bit 19)                                        */
#define GPIO_OTR_OTR19_Msk                (0x80000UL)               /*!< OTR19 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR20_Pos                (20UL)                    /*!< OTR20 (Bit 20)                                        */
#define GPIO_OTR_OTR20_Msk                (0x100000UL)              /*!< OTR20 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR21_Pos                (21UL)                    /*!< OTR21 (Bit 21)                                        */
#define GPIO_OTR_OTR21_Msk                (0x200000UL)              /*!< OTR21 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR22_Pos                (22UL)                    /*!< OTR22 (Bit 22)                                        */
#define GPIO_OTR_OTR22_Msk                (0x400000UL)              /*!< OTR22 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR23_Pos                (23UL)                    /*!< OTR23 (Bit 23)                                        */
#define GPIO_OTR_OTR23_Msk                (0x800000UL)              /*!< OTR23 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR24_Pos                (24UL)                    /*!< OTR24 (Bit 24)                                        */
#define GPIO_OTR_OTR24_Msk                (0x1000000UL)             /*!< OTR24 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR25_Pos                (25UL)                    /*!< OTR25 (Bit 25)                                        */
#define GPIO_OTR_OTR25_Msk                (0x2000000UL)             /*!< OTR25 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR26_Pos                (26UL)                    /*!< OTR26 (Bit 26)                                        */
#define GPIO_OTR_OTR26_Msk                (0x4000000UL)             /*!< OTR26 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR27_Pos                (27UL)                    /*!< OTR27 (Bit 27)                                        */
#define GPIO_OTR_OTR27_Msk                (0x8000000UL)             /*!< OTR27 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR28_Pos                (28UL)                    /*!< OTR28 (Bit 28)                                        */
#define GPIO_OTR_OTR28_Msk                (0x10000000UL)            /*!< OTR28 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR29_Pos                (29UL)                    /*!< OTR29 (Bit 29)                                        */
#define GPIO_OTR_OTR29_Msk                (0x20000000UL)            /*!< OTR29 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR30_Pos                (30UL)                    /*!< OTR30 (Bit 30)                                        */
#define GPIO_OTR_OTR30_Msk                (0x40000000UL)            /*!< OTR30 (Bitfield-Mask: 0x01)                           */
#define GPIO_OTR_OTR31_Pos                (31UL)                    /*!< OTR31 (Bit 31)                                        */
#define GPIO_OTR_OTR31_Msk                (0x80000000UL)            /*!< OTR31 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  IDR  ========================================================== */
#define GPIO_IDR_IDR0_Pos                 (0UL)                     /*!< IDR0 (Bit 0)                                          */
#define GPIO_IDR_IDR0_Msk                 (0x1UL)                   /*!< IDR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR1_Pos                 (1UL)                     /*!< IDR1 (Bit 1)                                          */
#define GPIO_IDR_IDR1_Msk                 (0x2UL)                   /*!< IDR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR2_Pos                 (2UL)                     /*!< IDR2 (Bit 2)                                          */
#define GPIO_IDR_IDR2_Msk                 (0x4UL)                   /*!< IDR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR3_Pos                 (3UL)                     /*!< IDR3 (Bit 3)                                          */
#define GPIO_IDR_IDR3_Msk                 (0x8UL)                   /*!< IDR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR4_Pos                 (4UL)                     /*!< IDR4 (Bit 4)                                          */
#define GPIO_IDR_IDR4_Msk                 (0x10UL)                  /*!< IDR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR5_Pos                 (5UL)                     /*!< IDR5 (Bit 5)                                          */
#define GPIO_IDR_IDR5_Msk                 (0x20UL)                  /*!< IDR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR6_Pos                 (6UL)                     /*!< IDR6 (Bit 6)                                          */
#define GPIO_IDR_IDR6_Msk                 (0x40UL)                  /*!< IDR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR7_Pos                 (7UL)                     /*!< IDR7 (Bit 7)                                          */
#define GPIO_IDR_IDR7_Msk                 (0x80UL)                  /*!< IDR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR8_Pos                 (8UL)                     /*!< IDR8 (Bit 8)                                          */
#define GPIO_IDR_IDR8_Msk                 (0x100UL)                 /*!< IDR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR9_Pos                 (9UL)                     /*!< IDR9 (Bit 9)                                          */
#define GPIO_IDR_IDR9_Msk                 (0x200UL)                 /*!< IDR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR10_Pos                (10UL)                    /*!< IDR10 (Bit 10)                                        */
#define GPIO_IDR_IDR10_Msk                (0x400UL)                 /*!< IDR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR11_Pos                (11UL)                    /*!< IDR11 (Bit 11)                                        */
#define GPIO_IDR_IDR11_Msk                (0x800UL)                 /*!< IDR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR12_Pos                (12UL)                    /*!< IDR12 (Bit 12)                                        */
#define GPIO_IDR_IDR12_Msk                (0x1000UL)                /*!< IDR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR13_Pos                (13UL)                    /*!< IDR13 (Bit 13)                                        */
#define GPIO_IDR_IDR13_Msk                (0x2000UL)                /*!< IDR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR14_Pos                (14UL)                    /*!< IDR14 (Bit 14)                                        */
#define GPIO_IDR_IDR14_Msk                (0x4000UL)                /*!< IDR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR15_Pos                (15UL)                    /*!< IDR15 (Bit 15)                                        */
#define GPIO_IDR_IDR15_Msk                (0x8000UL)                /*!< IDR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR16_Pos                (16UL)                    /*!< IDR16 (Bit 16)                                        */
#define GPIO_IDR_IDR16_Msk                (0x10000UL)               /*!< IDR16 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR17_Pos                (17UL)                    /*!< IDR17 (Bit 17)                                        */
#define GPIO_IDR_IDR17_Msk                (0x20000UL)               /*!< IDR17 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR18_Pos                (18UL)                    /*!< IDR18 (Bit 18)                                        */
#define GPIO_IDR_IDR18_Msk                (0x40000UL)               /*!< IDR18 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR19_Pos                (19UL)                    /*!< IDR19 (Bit 19)                                        */
#define GPIO_IDR_IDR19_Msk                (0x80000UL)               /*!< IDR19 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR20_Pos                (20UL)                    /*!< IDR20 (Bit 20)                                        */
#define GPIO_IDR_IDR20_Msk                (0x100000UL)              /*!< IDR20 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR21_Pos                (21UL)                    /*!< IDR21 (Bit 21)                                        */
#define GPIO_IDR_IDR21_Msk                (0x200000UL)              /*!< IDR21 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR22_Pos                (22UL)                    /*!< IDR22 (Bit 22)                                        */
#define GPIO_IDR_IDR22_Msk                (0x400000UL)              /*!< IDR22 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR23_Pos                (23UL)                    /*!< IDR23 (Bit 23)                                        */
#define GPIO_IDR_IDR23_Msk                (0x800000UL)              /*!< IDR23 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR24_Pos                (24UL)                    /*!< IDR24 (Bit 24)                                        */
#define GPIO_IDR_IDR24_Msk                (0x1000000UL)             /*!< IDR24 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR25_Pos                (25UL)                    /*!< IDR25 (Bit 25)                                        */
#define GPIO_IDR_IDR25_Msk                (0x2000000UL)             /*!< IDR25 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR26_Pos                (26UL)                    /*!< IDR26 (Bit 26)                                        */
#define GPIO_IDR_IDR26_Msk                (0x4000000UL)             /*!< IDR26 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR27_Pos                (27UL)                    /*!< IDR27 (Bit 27)                                        */
#define GPIO_IDR_IDR27_Msk                (0x8000000UL)             /*!< IDR27 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR28_Pos                (28UL)                    /*!< IDR28 (Bit 28)                                        */
#define GPIO_IDR_IDR28_Msk                (0x10000000UL)            /*!< IDR28 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR29_Pos                (29UL)                    /*!< IDR29 (Bit 29)                                        */
#define GPIO_IDR_IDR29_Msk                (0x20000000UL)            /*!< IDR29 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR30_Pos                (30UL)                    /*!< IDR30 (Bit 30)                                        */
#define GPIO_IDR_IDR30_Msk                (0x40000000UL)            /*!< IDR30 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR31_Pos                (31UL)                    /*!< IDR31 (Bit 31)                                        */
#define GPIO_IDR_IDR31_Msk                (0x80000000UL)            /*!< IDR31 (Bitfield-Mask: 0x01)                           */
/* =========================================================  IRQF  ========================================================== */
#define GPIO_IRQF_IRQF_Pos                (0UL)                     /*!< IRQF (Bit 0)                                          */
#define GPIO_IRQF_IRQF_Msk                (0xffffffffUL)            /*!< IRQF (Bitfield-Mask: 0xffffffff)                      */
#define GPIO_IRQF_IRQF0_Pos               (0UL)                     /*!< IRQF0 (Bit 0)                                         */
#define GPIO_IRQF_IRQF0_Msk               (0x1UL)                   /*!< IRQF0 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF1_Pos               (1UL)                     /*!< IRQF1 (Bit 1)                                         */
#define GPIO_IRQF_IRQF1_Msk               (0x2UL)                   /*!< IRQF1 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF2_Pos               (2UL)                     /*!< IRQF2 (Bit 2)                                         */
#define GPIO_IRQF_IRQF2_Msk               (0x4UL)                   /*!< IRQF2 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF3_Pos               (3UL)                     /*!< IRQF3 (Bit 3)                                         */
#define GPIO_IRQF_IRQF3_Msk               (0x8UL)                   /*!< IRQF3 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF4_Pos               (4UL)                     /*!< IRQF4 (Bit 4)                                         */
#define GPIO_IRQF_IRQF4_Msk               (0x10UL)                  /*!< IRQF4 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF5_Pos               (5UL)                     /*!< IRQF5 (Bit 5)                                         */
#define GPIO_IRQF_IRQF5_Msk               (0x20UL)                  /*!< IRQF5 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF6_Pos               (6UL)                     /*!< IRQF6 (Bit 6)                                         */
#define GPIO_IRQF_IRQF6_Msk               (0x40UL)                  /*!< IRQF6 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF7_Pos               (7UL)                     /*!< IRQF7 (Bit 7)                                         */
#define GPIO_IRQF_IRQF7_Msk               (0x80UL)                  /*!< IRQF7 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF8_Pos               (8UL)                     /*!< IRQF8 (Bit 8)                                         */
#define GPIO_IRQF_IRQF8_Msk               (0x100UL)                 /*!< IRQF8 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF9_Pos               (9UL)                     /*!< IRQF9 (Bit 9)                                         */
#define GPIO_IRQF_IRQF9_Msk               (0x200UL)                 /*!< IRQF9 (Bitfield-Mask: 0x01)                           */
#define GPIO_IRQF_IRQF10_Pos              (10UL)                    /*!< IRQF10 (Bit 10)                                       */
#define GPIO_IRQF_IRQF10_Msk              (0x400UL)                 /*!< IRQF10 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF11_Pos              (11UL)                    /*!< IRQF11 (Bit 11)                                       */
#define GPIO_IRQF_IRQF11_Msk              (0x800UL)                 /*!< IRQF11 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF12_Pos              (12UL)                    /*!< IRQF12 (Bit 12)                                       */
#define GPIO_IRQF_IRQF12_Msk              (0x1000UL)                /*!< IRQF12 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF13_Pos              (13UL)                    /*!< IRQF13 (Bit 13)                                       */
#define GPIO_IRQF_IRQF13_Msk              (0x2000UL)                /*!< IRQF13 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF14_Pos              (14UL)                    /*!< IRQF14 (Bit 14)                                       */
#define GPIO_IRQF_IRQF14_Msk              (0x4000UL)                /*!< IRQF14 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF15_Pos              (15UL)                    /*!< IRQF15 (Bit 15)                                       */
#define GPIO_IRQF_IRQF15_Msk              (0x8000UL)                /*!< IRQF15 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF16_Pos              (16UL)                    /*!< IRQF16 (Bit 16)                                       */
#define GPIO_IRQF_IRQF16_Msk              (0x10000UL)               /*!< IRQF16 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF17_Pos              (17UL)                    /*!< IRQF17 (Bit 17)                                       */
#define GPIO_IRQF_IRQF17_Msk              (0x20000UL)               /*!< IRQF17 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF18_Pos              (18UL)                    /*!< IRQF18 (Bit 18)                                       */
#define GPIO_IRQF_IRQF18_Msk              (0x40000UL)               /*!< IRQF18 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF19_Pos              (19UL)                    /*!< IRQF19 (Bit 19)                                       */
#define GPIO_IRQF_IRQF19_Msk              (0x80000UL)               /*!< IRQF19 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF20_Pos              (20UL)                    /*!< IRQF20 (Bit 20)                                       */
#define GPIO_IRQF_IRQF20_Msk              (0x100000UL)              /*!< IRQF20 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF21_Pos              (21UL)                    /*!< IRQF21 (Bit 21)                                       */
#define GPIO_IRQF_IRQF21_Msk              (0x200000UL)              /*!< IRQF21 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF22_Pos              (22UL)                    /*!< IRQF22 (Bit 22)                                       */
#define GPIO_IRQF_IRQF22_Msk              (0x400000UL)              /*!< IRQF22 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF23_Pos              (23UL)                    /*!< IRQF23 (Bit 23)                                       */
#define GPIO_IRQF_IRQF23_Msk              (0x800000UL)              /*!< IRQF23 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF24_Pos              (24UL)                    /*!< IRQF24 (Bit 24)                                       */
#define GPIO_IRQF_IRQF24_Msk              (0x1000000UL)             /*!< IRQF24 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF25_Pos              (25UL)                    /*!< IRQF25 (Bit 25)                                       */
#define GPIO_IRQF_IRQF25_Msk              (0x2000000UL)             /*!< IRQF25 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF26_Pos              (26UL)                    /*!< IRQF26 (Bit 26)                                       */
#define GPIO_IRQF_IRQF26_Msk              (0x4000000UL)             /*!< IRQF26 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF27_Pos              (27UL)                    /*!< IRQF27 (Bit 27)                                       */
#define GPIO_IRQF_IRQF27_Msk              (0x8000000UL)             /*!< IRQF27 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF28_Pos              (28UL)                    /*!< IRQF28 (Bit 28)                                       */
#define GPIO_IRQF_IRQF28_Msk              (0x10000000UL)            /*!< IRQF28 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF29_Pos              (29UL)                    /*!< IRQF29 (Bit 29)                                       */
#define GPIO_IRQF_IRQF29_Msk              (0x20000000UL)            /*!< IRQF29 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF30_Pos              (30UL)                    /*!< IRQF30 (Bit 30)                                       */
#define GPIO_IRQF_IRQF30_Msk              (0x40000000UL)            /*!< IRQF30 (Bitfield-Mask: 0x01)                          */
#define GPIO_IRQF_IRQF31_Pos              (31UL)                    /*!< IRQF31 (Bit 31)                                       */
#define GPIO_IRQF_IRQF31_Msk              (0x80000000UL)            /*!< IRQF31 (Bitfield-Mask: 0x01)                          */
/* =========================================================  DFLC  ========================================================== */
#define GPIO_DFL_RMDFL_Pos                (0UL)                     /*!< RMDFL (Bit 0)                                         */
#define GPIO_DFL_RMDFL_Msk                (0x1fUL)                  /*!< RMDFL (Bitfield-Mask: 0x1f)                           */
#define GPIO_DFL_LPDFL_Pos                (5UL)                     /*!< LPDFL (Bit 5)                                         */
#define GPIO_DFL_LPDFL_Msk                (0x3e0UL)                 /*!< LPDFL (Bitfield-Mask: 0x1f)                           */
/* =========================================================  LPDFC  ========================================================= */
#define GPIO_LPDFC_LPDFPS_Pos             (0UL)                     /*!< LPDFPS (Bit 0)                                        */
#define GPIO_LPDFC_LPDFPS_Msk             (0x1fUL)                  /*!< LPDFPS (Bitfield-Mask: 0x1f)                          */
#define GPIO_LPDFC_LPDFE_Pos              (5UL)                     /*!< LPDFE (Bit 5)                                         */
#define GPIO_LPDFC_LPDFE_Msk              (0x20UL)                  /*!< LPDFE (Bitfield-Mask: 0x01)                           */
/* =========================================================  PCR   ========================================================== */
#define GPIO_PCR_PUM_Pos                  (0UL)                     /*!< PUM (Bit 0)                                           */
#define GPIO_PCR_PUM_Msk                  (0x3UL)                   /*!< PUM (Bitfield-Mask: 0x03)                             */
#define GPIO_PCR_SRC_Pos                  (2UL)                     /*!< SRC  (Bit 2)                                          */
#define GPIO_PCR_SRC_Msk                  (0x4UL)                   /*!< SRC  (Bitfield-Mask: 0x01)                            */
#define GPIO_PCR_SMT_Pos                  (3UL)                     /*!< SMT (Bit 3)                                           */
#define GPIO_PCR_SMT_Msk                  (0x8UL)                   /*!< SMT (Bitfield-Mask: 0x01)                             */
#define GPIO_PCR_DSC_Pos                  (4UL)                     /*!< DSC  (Bit 4)                                          */
#define GPIO_PCR_DSC_Msk                  (0x10UL)                  /*!< DSC  (Bitfield-Mask: 0x01)                            */
#define GPIO_PCR_PMS_Pos                  (5UL)                     /*!< PMS (Bit 5)                                           */
#define GPIO_PCR_PMS_Msk                  (0x60UL)                  /*!< PMS (Bitfield-Mask: 0x03)                             */
#define GPIO_PCR_MUX_Pos                  (8UL)                     /*!< MUX (Bit 8)                                           */
#define GPIO_PCR_MUX_Msk                  (0x700UL)                 /*!< MUX (Bitfield-Mask: 0x07)                             */
#define GPIO_PCR_RMDFE_Pos                (12UL)                    /*!< RMDFE (Bit 12)                                        */
#define GPIO_PCR_RMDFE_Msk                (0x1000UL)                /*!< RMDFE (Bitfield-Mask: 0x01)                           */
#define GPIO_PCR_LKC_Pos                  (15UL)                    /*!< LKC  (Bit 15)                                         */
#define GPIO_PCR_LKC_Msk                  (0x8000UL)                /*!< LKC  (Bitfield-Mask: 0x01)                            */
#define GPIO_PCR_IRQT_Pos                 (16UL)                    /*!< IRQT  (Bit 16)                                        */
#define GPIO_PCR_IRQT_Msk                 (0x30000UL)               /*!< IRQT  (Bitfield-Mask: 0x03)                           */

/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define CRC_CTRL_TCRC_Pos                 (0UL)                     /*!< TCRC (Bit 0)                                          */
#define CRC_CTRL_TCRC_Msk                 (0x1UL)                   /*!< TCRC (Bitfield-Mask: 0x01)                            */
#define CRC_CTRL_TOTW_Pos                 (1UL)                     /*!< TOTW (Bit 1)                                          */
#define CRC_CTRL_TOTW_Msk                 (0x6UL)                   /*!< TOTW (Bitfield-Mask: 0x03)                            */
#define CRC_CTRL_TOTR_Pos                 (3UL)                     /*!< TOTR (Bit 3)                                          */
#define CRC_CTRL_TOTR_Msk                 (0x18UL)                  /*!< TOTR (Bitfield-Mask: 0x03)                            */
#define CRC_CTRL_XOR_Pos                  (5UL)                     /*!< XOR  (Bit 5)                                          */
#define CRC_CTRL_XOR_Msk                  (0x20UL)                  /*!< XOR  (Bitfield-Mask: 0x01)                            */
/* =========================================================  POLY  ========================================================== */
#define CRC_POLY_POLY_Pos                 (0UL)                     /*!< POLY (Bit 0)                                          */
#define CRC_POLY_POLY_Msk                 (0xffffffffUL)            /*!< POLY (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  SEED  ========================================================== */
#define CRC_SEED_SEED_Pos                 (0UL)                     /*!< SEED (Bit 0)                                          */
#define CRC_SEED_SEED_Msk                 (0xffffffffUL)            /*!< SEED (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DATA  ========================================================== */
#define CRC_DATA_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATA_DATA_Msk                 (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */




/* =========================================================================================================================== */
/* ================                                           CAN                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  RBUFF  ========================================================= */
/* =======================================================  ID&ESI  ========================================================== */
#define CAN_RBUFF_ID_STD_Pos              (0UL)
#define CAN_RBUFF_ID_STD_Msk              (0x7FFUL)
#define CAN_RBUFF_ID_EXT_Pos              (0UL)
#define CAN_RBUFF_ID_EXT_Msk              (0x1FFFFFFFUL)
#define CAN_RBUFF_ESI_Pos                 (31UL)
#define CAN_RBUFF_ESI_Msk                 (0x80000000UL)
/* =======================================================  CONTROL&STATUS  ================================================== */
#define CAN_RBUFF_DLC_Pos                 (0UL)
#define CAN_RBUFF_DLC_Msk                 (0xFUL)
#define CAN_RBUFF_BRS_Pos                 (4UL)
#define CAN_RBUFF_BRS_Msk                 (0x10UL)
#define CAN_RBUFF_FDF_Pos                 (5UL)
#define CAN_RBUFF_FDF_Msk                 (0x20UL)
#define CAN_RBUFF_RTR_Pos                 (6UL)
#define CAN_RBUFF_RTR_Msk                 (0x40UL)
#define CAN_RBUFF_IDE_Pos                 (7UL)
#define CAN_RBUFF_IDE_Msk                 (0x80UL)
#define CAN_RBUFF_TX_Pos                  (12UL)
#define CAN_RBUFF_TX_Msk                  (0x1000UL)
#define CAN_RBUFF_KOER_Pos                (13UL)
#define CAN_RBUFF_KOER_Msk                (0xE000UL)
/* =========================================================  TBUFF  ========================================================= */
/* =======================================================  ID&TTSEN  ======================================================== */
#define CAN_TBUFF_ID_STD_Pos              (0UL)
#define CAN_TBUFF_ID_STD_Msk              (0x1FFUL)
#define CAN_TBUFF_ID_EXT_Pos              (0UL)
#define CAN_TBUFF_ID_EXT_Msk              (0x1FFFFFFFUL)
#define CAN_TBUFF_TTSEN_Pos               (31UL)
#define CAN_TBUFF_TTSEN_Msk               (0x80000000UL)
/* =======================================================  CONTROL&STATUS  ================================================== */
#define CAN_TBUFF_DLC_Pos                 (0UL)
#define CAN_TBUFF_DLC_Msk                 (0xFUL)
#define CAN_TBUFF_BRS_Pos                 (4UL)
#define CAN_TBUFF_BRS_Msk                 (0x10UL)
#define CAN_TBUFF_FDF_Pos                 (5UL)
#define CAN_TBUFF_FDF_Msk                 (0x20UL)
#define CAN_TBUFF_RTR_Pos                 (6UL)
#define CAN_TBUFF_RTR_Msk                 (0x40UL)
#define CAN_TBUFF_IDE_Pos                 (7UL)
#define CAN_TBUFF_IDE_Msk                 (0x80UL)
/* =========================================================  CTRL0  ========================================================= */
#define CAN_CTRL0_BUSOFF_Pos              (0UL)                     /*!< BUSOFF (Bit 0)                                        */
#define CAN_CTRL0_BUSOFF_Msk              (0x1UL)                   /*!< BUSOFF (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_TACTIVE_Pos             (1UL)                     /*!< TACTIVE (Bit 1)                                       */
#define CAN_CTRL0_TACTIVE_Msk             (0x2UL)                   /*!< TACTIVE (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_RACTIVE_Pos             (2UL)                     /*!< RACTIVE (Bit 2)                                       */
#define CAN_CTRL0_RACTIVE_Msk             (0x4UL)                   /*!< RACTIVE (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_TSSS_Pos                (3UL)                     /*!< TSSS (Bit 3)                                          */
#define CAN_CTRL0_TSSS_Msk                (0x8UL)                   /*!< TSSS (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_TPSS_Pos                (4UL)                     /*!< TPSS (Bit 4)                                          */
#define CAN_CTRL0_TPSS_Msk                (0x10UL)                  /*!< TPSS (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LBMI_Pos                (5UL)                     /*!< LBMI (Bit 5)                                          */
#define CAN_CTRL0_LBMI_Msk                (0x20UL)                  /*!< LBMI (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LBME_Pos                (6UL)                     /*!< LBME (Bit 6)                                          */
#define CAN_CTRL0_LBME_Msk                (0x40UL)                  /*!< LBME (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_RESET_Pos               (7UL)                     /*!< RESET (Bit 7)                                         */
#define CAN_CTRL0_RESET_Msk               (0x80UL)                  /*!< RESET (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSA_Pos                 (8UL)                     /*!< TSA (Bit 8)                                           */
#define CAN_CTRL0_TSA_Msk                 (0x100UL)                 /*!< TSA (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TSALL_Pos               (9UL)                     /*!< TSALL (Bit 9)                                         */
#define CAN_CTRL0_TSALL_Msk               (0x200UL)                 /*!< TSALL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSONE_Pos               (10UL)                    /*!< TSONE (Bit 10)                                        */
#define CAN_CTRL0_TSONE_Msk               (0x400UL)                 /*!< TSONE (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TPA_Pos                 (11UL)                    /*!< TPA (Bit 11)                                          */
#define CAN_CTRL0_TPA_Msk                 (0x800UL)                 /*!< TPA (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TPE_Pos                 (12UL)                    /*!< TPE (Bit 12)                                          */
#define CAN_CTRL0_TPE_Msk                 (0x1000UL)                /*!< TPE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_STBY_Pos                (13UL)                    /*!< STBY (Bit 13)                                         */
#define CAN_CTRL0_STBY_Msk                (0x2000UL)                /*!< STBY (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LOM_Pos                 (14UL)                    /*!< LOM (Bit 14)                                          */
#define CAN_CTRL0_LOM_Msk                 (0x4000UL)                /*!< LOM (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TBSEL_Pos               (15UL)                    /*!< TBSEL (Bit 15)                                        */
#define CAN_CTRL0_TBSEL_Msk               (0x8000UL)                /*!< TBSEL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSSTAT_Pos              (16UL)                    /*!< TSSTAT (Bit 16)                                       */
#define CAN_CTRL0_TSSTAT_Msk              (0x30000UL)               /*!< TSSTAT (Bitfield-Mask: 0x03)                          */
#define CAN_CTRL0_BOFFREC_Pos             (18UL)                    /*!< BOFFREC (Bit 18)                                      */
#define CAN_CTRL0_BOFFREC_Msk             (0x40000UL)               /*!< BOFFREC (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_CANFDEN_Pos             (19UL)                    /*!< CANFDEN (Bit 19)                                      */
#define CAN_CTRL0_CANFDEN_Msk             (0x80000UL)               /*!< CANFDEN (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_TSMODE_Pos              (21UL)                    /*!< TSMODE (Bit 21)                                       */
#define CAN_CTRL0_TSMODE_Msk              (0x200000UL)              /*!< TSMODE (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_TSNEXT_Pos              (22UL)                    /*!< TSNEXT (Bit 22)                                       */
#define CAN_CTRL0_TSNEXT_Msk              (0x400000UL)              /*!< TSNEXT (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_FDISO_Pos               (23UL)                    /*!< FDISO (Bit 23)                                        */
#define CAN_CTRL0_FDISO_Msk               (0x800000UL)              /*!< FDISO (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_RSTAT_Pos               (24UL)                    /*!< RSTAT (Bit 24)                                        */
#define CAN_CTRL0_RSTAT_Msk               (0x3000000UL)             /*!< RSTAT (Bitfield-Mask: 0x03)                           */
#define CAN_CTRL0_RBALL_Pos               (27UL)                    /*!< RBALL (Bit 27)                                        */
#define CAN_CTRL0_RBALL_Msk               (0x8000000UL)             /*!< RBALL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_RREL_Pos                (28UL)                    /*!< RREL (Bit 28)                                         */
#define CAN_CTRL0_RREL_Msk                (0x10000000UL)            /*!< RREL (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_ROV_Pos                 (29UL)                    /*!< ROV (Bit 29)                                          */
#define CAN_CTRL0_ROV_Msk                 (0x20000000UL)            /*!< ROV (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_ROM_Pos                 (30UL)                    /*!< ROM (Bit 30)                                          */
#define CAN_CTRL0_ROM_Msk                 (0x40000000UL)            /*!< ROM (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_SACK_Pos                (31UL)                    /*!< SACK (Bit 31)                                         */
#define CAN_CTRL0_SACK_Msk                (0x80000000UL)            /*!< SACK (Bitfield-Mask: 0x01)                            */
/* =========================================================  CTRL1  ========================================================= */
#define CAN_CTRL1_TSFF_Pos                (0UL)                     /*!< TSFF (Bit 0)                                          */
#define CAN_CTRL1_TSFF_Msk                (0x1UL)                   /*!< TSFF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EIE_Pos                 (1UL)                     /*!< EIE (Bit 1)                                           */
#define CAN_CTRL1_EIE_Msk                 (0x2UL)                   /*!< EIE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_TSIE_Pos                (2UL)                     /*!< TSIE (Bit 2)                                          */
#define CAN_CTRL1_TSIE_Msk                (0x4UL)                   /*!< TSIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_TPIE_Pos                (3UL)                     /*!< TPIE (Bit 3)                                          */
#define CAN_CTRL1_TPIE_Msk                (0x8UL)                   /*!< TPIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RAFIE_Pos               (4UL)                     /*!< RAFIE (Bit 4)                                         */
#define CAN_CTRL1_RAFIE_Msk               (0x10UL)                  /*!< RAFIE (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_RFIE_Pos                (5UL)                     /*!< RFIE (Bit 5)                                          */
#define CAN_CTRL1_RFIE_Msk                (0x20UL)                  /*!< RFIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ROIE_Pos                (6UL)                     /*!< ROIE (Bit 6)                                          */
#define CAN_CTRL1_ROIE_Msk                (0x40UL)                  /*!< ROIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RIE_Pos                 (7UL)                     /*!< RIE (Bit 7)                                           */
#define CAN_CTRL1_RIE_Msk                 (0x80UL)                  /*!< RIE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_AIF_Pos                 (8UL)                     /*!< AIF (Bit 8)                                           */
#define CAN_CTRL1_AIF_Msk                 (0x100UL)                 /*!< AIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_EIF_Pos                 (9UL)                     /*!< EIF (Bit 9)                                           */
#define CAN_CTRL1_EIF_Msk                 (0x200UL)                 /*!< EIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_TSIF_Pos                (10UL)                    /*!< TSIF (Bit 10)                                         */
#define CAN_CTRL1_TSIF_Msk                (0x400UL)                 /*!< TSIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_TPIF_Pos                (11UL)                    /*!< TPIF (Bit 11)                                         */
#define CAN_CTRL1_TPIF_Msk                (0x800UL)                 /*!< TPIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RAFIF_Pos               (12UL)                    /*!< RAFIF (Bit 12)                                        */
#define CAN_CTRL1_RAFIF_Msk               (0x1000UL)                /*!< RAFIF (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_RFIF_Pos                (13UL)                    /*!< RFIF (Bit 13)                                         */
#define CAN_CTRL1_RFIF_Msk                (0x2000UL)                /*!< RFIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ROIF_Pos                (14UL)                    /*!< ROIF (Bit 14)                                         */
#define CAN_CTRL1_ROIF_Msk                (0x4000UL)                /*!< ROIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RIF_Pos                 (15UL)                    /*!< RIF (Bit 15)                                          */
#define CAN_CTRL1_RIF_Msk                 (0x8000UL)                /*!< RIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_BEIF_Pos                (16UL)                    /*!< BEIF (Bit 16)                                         */
#define CAN_CTRL1_BEIF_Msk                (0x10000UL)               /*!< BEIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_BEIE_Pos                (17UL)                    /*!< BEIE (Bit 17)                                         */
#define CAN_CTRL1_BEIE_Msk                (0x20000UL)               /*!< BEIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ALIF_Pos                (18UL)                    /*!< ALIF (Bit 18)                                         */
#define CAN_CTRL1_ALIF_Msk                (0x40000UL)               /*!< ALIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ALIE_Pos                (19UL)                    /*!< ALIE (Bit 19)                                         */
#define CAN_CTRL1_ALIE_Msk                (0x80000UL)               /*!< ALIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPIF_Pos                (20UL)                    /*!< EPIF (Bit 20)                                         */
#define CAN_CTRL1_EPIF_Msk                (0x100000UL)              /*!< EPIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPIE_Pos                (21UL)                    /*!< EPIE (Bit 21)                                         */
#define CAN_CTRL1_EPIE_Msk                (0x200000UL)              /*!< EPIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPASS_Pos               (22UL)                    /*!< EPASS (Bit 22)                                        */
#define CAN_CTRL1_EPASS_Msk               (0x400000UL)              /*!< EPASS (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_EWARN_Pos               (23UL)                    /*!< EWARN (Bit 23)                                        */
#define CAN_CTRL1_EWARN_Msk               (0x800000UL)              /*!< EWARN (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_EWL_Pos                 (24UL)                    /*!< EWL (Bit 24)                                          */
#define CAN_CTRL1_EWL_Msk                 (0xf000000UL)             /*!< EWL (Bitfield-Mask: 0x0f)                             */
#define CAN_CTRL1_AFWL_Pos                (28UL)                    /*!< AFWL (Bit 28)                                         */
#define CAN_CTRL1_AFWL_Msk                (0xf0000000UL)            /*!< AFWL (Bitfield-Mask: 0x0f)                            */
/* =======================================================  SBITRATE  ======================================================== */
#define CAN_SBITRATE_S_SEG_1_Pos          (0UL)                     /*!< S_SEG_1 (Bit 0)                                       */
#define CAN_SBITRATE_S_SEG_1_Msk          (0xffUL)                  /*!< S_SEG_1 (Bitfield-Mask: 0xff)                         */
#define CAN_SBITRATE_S_SEG_2_Pos          (8UL)                     /*!< S_SEG_2 (Bit 8)                                       */
#define CAN_SBITRATE_S_SEG_2_Msk          (0x7f00UL)                /*!< S_SEG_2 (Bitfield-Mask: 0x7f)                         */
#define CAN_SBITRATE_S_SJW_Pos            (16UL)                    /*!< S_SJW (Bit 16)                                        */
#define CAN_SBITRATE_S_SJW_Msk            (0x7f0000UL)              /*!< S_SJW (Bitfield-Mask: 0x7f)                           */
#define CAN_SBITRATE_S_PRESC_Pos          (24UL)                    /*!< S_PRESC (Bit 24)                                      */
#define CAN_SBITRATE_S_PRESC_Msk          (0xff000000UL)            /*!< S_PRESC (Bitfield-Mask: 0xff)                         */
/* =======================================================  FBITRATE  ======================================================== */
#define CAN_FBITRATE_f_SEG_1_Pos          (0UL)                     /*!< f_SEG_1 (Bit 0)                                       */
#define CAN_FBITRATE_f_SEG_1_Msk          (0xffUL)                  /*!< f_SEG_1 (Bitfield-Mask: 0xff)                         */
#define CAN_FBITRATE_f_SEG_2_Pos          (8UL)                     /*!< f_SEG_2 (Bit 8)                                       */
#define CAN_FBITRATE_f_SEG_2_Msk          (0x7f00UL)                /*!< f_SEG_2 (Bitfield-Mask: 0x7f)                         */
#define CAN_FBITRATE_f_SJW_Pos            (16UL)                    /*!< f_SJW (Bit 16)                                        */
#define CAN_FBITRATE_f_SJW_Msk            (0x7f0000UL)              /*!< f_SJW (Bitfield-Mask: 0x7f)                           */
#define CAN_FBITRATE_f_PRESC_Pos          (24UL)                    /*!< f_PRESC (Bit 24)                                      */
#define CAN_FBITRATE_f_PRESC_Msk          (0xff000000UL)            /*!< f_PRESC (Bitfield-Mask: 0xff)                         */
/* ========================================================  ERRINFO  ======================================================== */
#define CAN_ERRINFO_ALC_Pos               (0UL)                     /*!< ALC (Bit 0)                                           */
#define CAN_ERRINFO_ALC_Msk               (0x1fUL)                  /*!< ALC (Bitfield-Mask: 0x1f)                             */
#define CAN_ERRINFO_KOER_Pos              (5UL)                     /*!< KOER (Bit 5)                                          */
#define CAN_ERRINFO_KOER_Msk              (0xe0UL)                  /*!< KOER (Bitfield-Mask: 0x07)                            */
#define CAN_ERRINFO_SSPOFF_Pos            (8UL)                     /*!< SSPOFF (Bit 8)                                        */
#define CAN_ERRINFO_SSPOFF_Msk            (0x7f00UL)                /*!< SSPOFF (Bitfield-Mask: 0x7f)                          */
#define CAN_ERRINFO_TDCEN_Pos             (15UL)                    /*!< TDCEN (Bit 15)                                        */
#define CAN_ERRINFO_TDCEN_Msk             (0x8000UL)                /*!< TDCEN (Bitfield-Mask: 0x01)                           */
#define CAN_ERRINFO_RECNT_Pos             (16UL)                    /*!< RECNT (Bit 16)                                        */
#define CAN_ERRINFO_RECNT_Msk             (0xff0000UL)              /*!< RECNT (Bitfield-Mask: 0xff)                           */
#define CAN_ERRINFO_TECNT_Pos             (24UL)                    /*!< TECNT (Bit 24)                                        */
#define CAN_ERRINFO_TECNT_Msk             (0xff000000UL)            /*!< TECNT (Bitfield-Mask: 0xff)                           */
/* ========================================================  ACFCTRL0  ======================================================= */
#define CAN_ACFCTRL0_ACFADR_Pos           (0UL)                     /*!< ACFADR (Bit 0)                                        */
#define CAN_ACFCTRL0_ACFADR_Msk           (0x1fUL)                   /*!< ACFADR (Bitfield-Mask: 0x0f)                         */
#define CAN_ACFCTRL0_SELMASK_Pos          (5UL)                     /*!< SELMASK (Bit 5)                                       */
#define CAN_ACFCTRL0_SELMASK_Msk          (0x20UL)                  /*!< SELMASK (Bitfield-Mask: 0x01)                         */
#define CAN_ACFCTRL0_TIMEEN_Pos           (8UL)                     /*!< TIMEEN (Bit 8)                                        */
#define CAN_ACFCTRL0_TIMEEN_Msk           (0x100UL)                 /*!< TIMEEN (Bitfield-Mask: 0x01)                          */
#define CAN_ACFCTRL0_TIMEPOS_Pos          (9UL)                     /*!< TIMEPOS (Bit 9)                                       */
#define CAN_ACFCTRL0_TIMEPOS_Msk          (0x200UL)                 /*!< TIMEPOS (Bitfield-Mask: 0x01)                         */
#define CAN_ACFCTRL0_ACFEN0_Pos           (16UL)                    /*!< ACFEN0 (Bit 16)                                       */
#define CAN_ACFCTRL0_ACFEN0_Msk           (0xffff0000UL)            /*!< ACFEN 0(Bitfield-Mask: 0xffff)                        */
/* ========================================================  ACFCTRL1  ======================================================= */
#define CAN_ACFCTRL1_ACFEN1_Pos           (0UL)                     /*!< ACFEN1 (Bit 0)                                        */
#define CAN_ACFCTRL1_ACFEN1_Msk           (0x000000ffUL)            /*!< ACFEN1 (Bitfield-Mask: 0xffff)                        */
/* ==========================================================  ACF  ========================================================== */
#define CAN_ACF_ACODE_Pos                 (0UL)                     /*!< ACODE (Bit 0)                                         */
#define CAN_ACF_ACODE_Msk                 (0x1fffffffUL)            /*!< ACODE (Bitfield-Mask: 0x1fffffff)                     */
#define CAN_ACF_AIDE_Pos                  (29UL)                    /*!< AIDE (Bit 29)                                         */
#define CAN_ACF_AIDE_Msk                  (0x20000000UL)            /*!< AIDE (Bitfield-Mask: 0x01)                            */
#define CAN_ACF_AIDEE_Pos                 (30UL)                    /*!< AIDEE (Bit 30)                                        */
#define CAN_ACF_AIDEE_Msk                 (0x40000000UL)            /*!< AIDEE (Bitfield-Mask: 0x01)                           */
/* ========================================================  VERSION  ======================================================== */
#define CAN_VERSION_VERSION_Pos           (0UL)                     /*!< VERSION (Bit 0)                                       */
#define CAN_VERSION_VERSION_Msk           (0xffffUL)                /*!< VERSION (Bitfield-Mask: 0xffff)                       */

/* =========================================================================================================================== */
/* ================                                            HSM                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  HHWE  ========================================================== */
#define HSM_HHWE_HDSBC_Pos                (0UL)                     /*!< HDSBC (Bit 0)                                         */
#define HSM_HHWE_HDSBC_Msk                (0x1UL)                   /*!< HDSBC (Bitfield-Mask: 0x01)                           */
#define HSM_HHWE_SOCAHBE_Pos              (1UL)                     /*!< SOCAHBE (Bit 1)                                       */
#define HSM_HHWE_SOCAHBE_Msk              (0x2UL)                   /*!< SOCAHBE (Bitfield-Mask: 0x01)                         */
#define HSM_HHWE_HWDGT_Pos                (2UL)                     /*!< HWDGT (Bit 2)                                         */
#define HSM_HHWE_HWDGT_Msk                (0x4UL)                   /*!< HWDGT (Bitfield-Mask: 0x01)                           */
#define HSM_HHWE_HDNCE_Pos                (3UL)                     /*!< HDNCE (Bit 3)                                         */
#define HSM_HHWE_HDNCE_Msk                (0x8UL)                   /*!< HDNCE (Bitfield-Mask: 0x01)                           */
#define HSM_HHWE_THTF_Pos                 (4UL)                     /*!< THTF (Bit 4)                                          */
#define HSM_HHWE_THTF_Msk                 (0x10UL)                  /*!< THTF (Bitfield-Mask: 0x01)                            */
#define HSM_HHWE_THTFRT_Pos               (5UL)                     /*!< THTFRT (Bit 5)                                        */
#define HSM_HHWE_THTFRT_Msk               (0x20UL)                  /*!< THTFRT (Bitfield-Mask: 0x01)                          */
#define HSM_HHWE_THTFRP_Pos               (6UL)                     /*!< THTFRP (Bit 6)                                        */
#define HSM_HHWE_THTFRP_Msk               (0x40UL)                  /*!< THTFRP (Bitfield-Mask: 0x01)                          */
#define HSM_HHWE_OKCE_Pos                 (7UL)                     /*!< OKCE (Bit 7)                                          */
#define HSM_HHWE_OKCE_Msk                 (0x80UL)                  /*!< OKCE (Bitfield-Mask: 0x01)                            */
/* =========================================================  HEIE  ========================================================== */
#define HSM_HEIE_HDSBCIE_Pos              (0UL)                     /*!< HDSBCIE (Bit 0)                                       */
#define HSM_HEIE_HDSBCIE_Msk              (0x1UL)                   /*!< HDSBCIE (Bitfield-Mask: 0x01)                         */
#define HSM_HEIE_HDNCEIE_Pos              (1UL)                     /*!< HDNCEIE (Bit 1)                                       */
#define HSM_HEIE_HDNCEIE_Msk              (0x2UL)                   /*!< HDNCEIE (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                            HSM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ESR  ========================================================== */
#define HSM_ESR_HDSBC_Pos                 (0UL)                     /*!< HDSBC (Bit 0)                                         */
#define HSM_ESR_HDSBC_Msk                 (0x1UL)                   /*!< HDSBC (Bitfield-Mask: 0x01)                           */
#define HSM_ESR_HWDGT_Pos                 (2UL)                     /*!< HWDGT (Bit 2)                                         */
#define HSM_ESR_HWDGT_Msk                 (0x4UL)                   /*!< HWDGT (Bitfield-Mask: 0x01)                           */
#define HSM_ESR_HDNCE_Pos                 (3UL)                     /*!< HDNCE (Bit 3)                                         */
#define HSM_ESR_HDNCE_Msk                 (0x8UL)                   /*!< HDNCE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  EIE  ========================================================== */
#define HSM_EIE_HDSBCIE_Pos               (0UL)                     /*!< HDSBCIE (Bit 0)                                       */
#define HSM_EIE_HDSBCIE_Msk               (0x1UL)                   /*!< HDSBCIE (Bitfield-Mask: 0x01)                         */
/* ========================================================  FWSTA0  ========================================================= */
#define HSM_FWSTA0_BSY_Pos                (0UL)                     /*!< BSY (Bit 0)                                           */
#define HSM_FWSTA0_BSY_Msk                (0x1UL)                   /*!< BSY (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_SB_Pos                 (1UL)                     /*!< SB (Bit 1)                                            */
#define HSM_FWSTA0_SB_Msk                 (0x2UL)                   /*!< SB (Bitfield-Mask: 0x01)                              */
#define HSM_FWSTA0_BIN_Pos                (2UL)                     /*!< BIN (Bit 2)                                           */
#define HSM_FWSTA0_BIN_Msk                (0x4UL)                   /*!< BIN (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_BFN_Pos                (3UL)                     /*!< BFN (Bit 3)                                           */
#define HSM_FWSTA0_BFN_Msk                (0x8UL)                   /*!< BFN (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_BOK_Pos                (4UL)                     /*!< BOK (Bit 4)                                           */
#define HSM_FWSTA0_BOK_Msk                (0x10UL)                  /*!< BOK (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_RIN_Pos                (5UL)                     /*!< RIN (Bit 5)                                           */
#define HSM_FWSTA0_RIN_Msk                (0x20UL)                  /*!< RIN (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_EDB_Pos                (6UL)                     /*!< EDB (Bit 6)                                           */
#define HSM_FWSTA0_EDB_Msk                (0x40UL)                  /*!< EDB (Bitfield-Mask: 0x01)                             */
#define HSM_FWSTA0_IDB_Pos                (7UL)                     /*!< IDB (Bit 7)                                           */
#define HSM_FWSTA0_IDB_Msk                (0x80UL)                  /*!< IDB (Bitfield-Mask: 0x01)                             */
/* ========================================================  FWSTA1  ========================================================= */
#define HSM_FWSTA1_FW_VERSION_Pos         (0UL)                     /*!< FW_VERSION (Bit 0)                                    */
#define HSM_FWSTA1_FW_VERSION_Msk         (0xffffffffUL)            /*!< FW_VERSION (Bitfield-Mask: 0xffffffff)                */
/* ========================================================  DBGSTA  ========================================================= */
#define HSM_DBGSTA_HSMDBG_Pos             (0UL)                     /*!< HSMDBG (Bit 0)                                        */
#define HSM_DBGSTA_HSMDBG_Msk             (0x1UL)                   /*!< HSMDBG (Bitfield-Mask: 0x01)                          */
#define HSM_DBGSTA_SOCDBG_Pos             (1UL)                     /*!< SOCDBG (Bit 1)                                        */
#define HSM_DBGSTA_SOCDBG_Msk             (0x2UL)                   /*!< SOCDBG (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                            MB                                             ================ */
/* =========================================================================================================================== */

/* =======================================================  S2H_INFO0  ======================================================= */
#define MB_S2H_INFO0_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO0_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO1  ======================================================= */
#define MB_S2H_INFO1_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO1_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO2  ======================================================= */
#define MB_S2H_INFO2_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO2_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO3  ======================================================= */
#define MB_S2H_INFO3_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO3_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO4  ======================================================= */
#define MB_S2H_INFO4_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO4_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO5  ======================================================= */
#define MB_S2H_INFO5_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO5_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO6  ======================================================= */
#define MB_S2H_INFO6_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO6_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO7  ======================================================= */
#define MB_S2H_INFO7_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO7_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO8  ======================================================= */
#define MB_S2H_INFO8_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO8_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_INFO9  ======================================================= */
#define MB_S2H_INFO9_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO9_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO10  ======================================================= */
#define MB_S2H_INFO10_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO10_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO11  ======================================================= */
#define MB_S2H_INFO11_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO11_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO12  ======================================================= */
#define MB_S2H_INFO12_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO12_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO13  ======================================================= */
#define MB_S2H_INFO13_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO13_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO14  ======================================================= */
#define MB_S2H_INFO14_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO14_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  S2H_INFO15  ======================================================= */
#define MB_S2H_INFO15_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_S2H_INFO15_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO0  ======================================================= */
#define MB_H2S_INFO0_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO0_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO1  ======================================================= */
#define MB_H2S_INFO1_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO1_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO2  ======================================================= */
#define MB_H2S_INFO2_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO2_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO3  ======================================================= */
#define MB_H2S_INFO3_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO3_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO4  ======================================================= */
#define MB_H2S_INFO4_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO4_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO5  ======================================================= */
#define MB_H2S_INFO5_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO5_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO6  ======================================================= */
#define MB_H2S_INFO6_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO6_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO7  ======================================================= */
#define MB_H2S_INFO7_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO7_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO8  ======================================================= */
#define MB_H2S_INFO8_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO8_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  H2S_INFO9  ======================================================= */
#define MB_H2S_INFO9_INFO_Pos             (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO9_INFO_Msk             (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO10  ======================================================= */
#define MB_H2S_INFO10_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO10_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO11  ======================================================= */
#define MB_H2S_INFO11_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO11_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO12  ======================================================= */
#define MB_H2S_INFO12_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO12_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO13  ======================================================= */
#define MB_H2S_INFO13_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO13_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO14  ======================================================= */
#define MB_H2S_INFO14_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO14_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  H2S_INFO15  ======================================================= */
#define MB_H2S_INFO15_INFO_Pos            (0UL)                     /*!< INFO (Bit 0)                                          */
#define MB_H2S_INFO15_INFO_Msk            (0xffffffffUL)            /*!< INFO (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  S2H_NOTE  ======================================================== */
#define MB_S2H_NOTE_NOTE_Pos              (0UL)                     /*!< NOTE (Bit 0)                                          */
#define MB_S2H_NOTE_NOTE_Msk              (0x3fffffffUL)            /*!< NOTE (Bitfield-Mask: 0x3fffffff)                      */
/* =======================================================  H2S_NOTE  ======================================================== */
#define MB_H2S_NOTE_NOTE_Pos              (0UL)                     /*!< NOTE (Bit 0)                                          */
#define MB_H2S_NOTE_NOTE_Msk              (0x3fffffffUL)            /*!< NOTE (Bitfield-Mask: 0x3fffffff)                      */
/* ======================================================  S2H_SOC_INT  ====================================================== */
#define MB_S2H_SOC_INT_S2H_SOC_INT_Pos    (0UL)                     /*!< S2H_SOC_INT (Bit 0)                                   */
#define MB_S2H_SOC_INT_S2H_SOC_INT_Msk    (0x3fffffffUL)            /*!< S2H_SOC_INT (Bitfield-Mask: 0x3fffffff)               */
#define MB_S2H_SOC_INT_S2H_SOC_COL_INT_Pos (31UL)                   /*!< S2H_SOC_COL_INT (Bit 31)                              */
#define MB_S2H_SOC_INT_S2H_SOC_COL_INT_Msk (0x80000000UL)           /*!< S2H_SOC_COL_INT (Bitfield-Mask: 0x01)                 */
/* ====================================================  S2H_SOC_INT_EN  ===================================================== */
#define MB_S2H_SOC_INT_EN_S2H_SOC_INT_EN_Pos (0UL)                  /*!< S2H_SOC_INT_EN (Bit 0)                                */
#define MB_S2H_SOC_INT_EN_S2H_SOC_INT_EN_Msk (0x3fffffffUL)         /*!< S2H_SOC_INT_EN (Bitfield-Mask: 0x3fffffff)            */
#define MB_S2H_SOC_INT_EN_S2H_SOC_COL_INT_EN_Pos (31UL)             /*!< S2H_SOC_COL_INT_EN (Bit 31)                           */
#define MB_S2H_SOC_INT_EN_S2H_SOC_COL_INT_EN_Msk (0x80000000UL)     /*!< S2H_SOC_COL_INT_EN (Bitfield-Mask: 0x01)              */
/* ======================================================  S2H_HSM_INT  ====================================================== */
#define MB_S2H_HSM_INT_S2H_HSM_INT_Pos    (0UL)                     /*!< S2H_HSM_INT (Bit 0)                                   */
#define MB_S2H_HSM_INT_S2H_HSM_INT_Msk    (0x3fffffffUL)            /*!< S2H_HSM_INT (Bitfield-Mask: 0x3fffffff)               */
#define MB_S2H_HSM_INT_S2H_SOC_COL_INT_Pos (31UL)                   /*!< S2H_SOC_COL_INT (Bit 31)                              */
#define MB_S2H_HSM_INT_S2H_SOC_COL_INT_Msk (0x80000000UL)           /*!< S2H_SOC_COL_INT (Bitfield-Mask: 0x01)                 */
/* ====================================================  S2H_HSM_INT_EN  ===================================================== */
#define MB_S2H_HSM_INT_EN_S2H_HSM_INT_EN_Pos (0UL)                  /*!< S2H_HSM_INT_EN (Bit 0)                                */
#define MB_S2H_HSM_INT_EN_S2H_HSM_INT_EN_Msk (0x3fffffffUL)         /*!< S2H_HSM_INT_EN (Bitfield-Mask: 0x3fffffff)            */
#define MB_S2H_HSM_INT_EN_S2H_HSM_COL_INT_EN_Pos (31UL)             /*!< S2H_HSM_COL_INT_EN (Bit 31)                           */
#define MB_S2H_HSM_INT_EN_S2H_HSM_COL_INT_EN_Msk (0x80000000UL)     /*!< S2H_HSM_COL_INT_EN (Bitfield-Mask: 0x01)              */
/* ======================================================  H2S_SOC_INT  ====================================================== */
#define MB_H2S_SOC_INT_H2S_SOC_INT_Pos    (0UL)                     /*!< H2S_SOC_INT (Bit 0)                                   */
#define MB_H2S_SOC_INT_H2S_SOC_INT_Msk    (0x3fffffffUL)            /*!< H2S_SOC_INT (Bitfield-Mask: 0x3fffffff)               */
#define MB_H2S_SOC_INT_H2S_SOC_COL_INT_Pos (31UL)                   /*!< H2S_SOC_COL_INT (Bit 31)                              */
#define MB_H2S_SOC_INT_H2S_SOC_COL_INT_Msk (0x80000000UL)           /*!< H2S_SOC_COL_INT (Bitfield-Mask: 0x01)                 */
/* ====================================================  H2S_SOC_INT_EN  ===================================================== */
#define MB_H2S_SOC_INT_EN_H2S_SOC_INT_EN_Pos (0UL)                  /*!< H2S_SOC_INT_EN (Bit 0)                                */
#define MB_H2S_SOC_INT_EN_H2S_SOC_INT_EN_Msk (0x3fffffffUL)         /*!< H2S_SOC_INT_EN (Bitfield-Mask: 0x3fffffff)            */
#define MB_H2S_SOC_INT_EN_H2S_SOC_COL_INT_EN_Pos (31UL)             /*!< H2S_SOC_COL_INT_EN (Bit 31)                           */
#define MB_H2S_SOC_INT_EN_H2S_SOC_COL_INT_EN_Msk (0x80000000UL)     /*!< H2S_SOC_COL_INT_EN (Bitfield-Mask: 0x01)              */
/* ======================================================  H2S_HSM_INT  ====================================================== */
#define MB_H2S_HSM_INT_H2S_HSM_INT_Pos    (0UL)                     /*!< H2S_HSM_INT (Bit 0)                                   */
#define MB_H2S_HSM_INT_H2S_HSM_INT_Msk    (0x3fffffffUL)            /*!< H2S_HSM_INT (Bitfield-Mask: 0x3fffffff)               */
#define MB_H2S_HSM_INT_H2S_SOC_COL_INT_Pos (31UL)                   /*!< H2S_SOC_COL_INT (Bit 31)                              */
#define MB_H2S_HSM_INT_H2S_SOC_COL_INT_Msk (0x80000000UL)           /*!< H2S_SOC_COL_INT (Bitfield-Mask: 0x01)                 */
/* ====================================================  H2S_HSM_INT_EN  ===================================================== */
#define MB_H2S_HSM_INT_EN_H2S_HSM_INT_EN_Pos (0UL)                  /*!< H2S_HSM_INT_EN (Bit 0)                                */
#define MB_H2S_HSM_INT_EN_H2S_HSM_INT_EN_Msk (0x3fffffffUL)         /*!< H2S_HSM_INT_EN (Bitfield-Mask: 0x3fffffff)            */
#define MB_H2S_HSM_INT_EN_H2S_HSM_COL_INT_EN_Pos (31UL)             /*!< H2S_HSM_COL_INT_EN (Bit 31)                           */
#define MB_H2S_HSM_INT_EN_H2S_HSM_COL_INT_EN_Msk (0x80000000UL)     /*!< H2S_HSM_COL_INT_EN (Bitfield-Mask: 0x01)              */
/* ======================================================  HSM_STATUS0  ====================================================== */
#define MBOX_STATUS0_HWBD_Pos             (0UL)                     /*!< HWBD (Bit 0)                                          */
#define MBOX_STATUS0_HWBD_Msk             (0x1UL)                   /*!< HWBD (Bitfield-Mask: 0x01)                            */
#define MBOX_STATUS0_HWBE_Pos             (1UL)                     /*!< HWBE (Bit 1)                                          */
#define MBOX_STATUS0_HWBE_Msk             (0x2UL)                   /*!< HWBE (Bitfield-Mask: 0x01)                            */
#define MBOX_STATUS0_FWBD_Pos             (2UL)                     /*!< FWBD (Bit 2)                                          */
#define MBOX_STATUS0_FWBD_Msk             (0x4UL)                   /*!< FWBD (Bitfield-Mask: 0x01)                            */
#define MBOX_STATUS0_FWBE_Pos             (3UL)                     /*!< FWBE (Bit 3)                                          */
#define MBOX_STATUS0_FWBE_Msk             (0x8UL)                   /*!< FWBE (Bitfield-Mask: 0x01)                            */
#define MBOX_STATUS0_LC_TEST_Pos          (8UL)                     /*!< LC_TEST (Bit 8)                                       */
#define MBOX_STATUS0_LC_TEST_Msk          (0x100UL)                 /*!< LC_TEST (Bitfield-Mask: 0x01)                         */
#define MBOX_STATUS0_LC_DEV_Pos           (9UL)                     /*!< LC_DEV (Bit 9)                                        */
#define MBOX_STATUS0_LC_DEV_Msk           (0x200UL)                 /*!< LC_DEV (Bitfield-Mask: 0x01)                          */
#define MBOX_STATUS0_LC_MANU_Pos          (10UL)                    /*!< LC_MANU (Bit 10)                                      */
#define MBOX_STATUS0_LC_MANU_Msk          (0x400UL)                 /*!< LC_MANU (Bitfield-Mask: 0x01)                         */
#define MBOX_STATUS0_LC_USER_Pos          (11UL)                    /*!< LC_USER (Bit 11)                                      */
#define MBOX_STATUS0_LC_USER_Msk          (0x800UL)                 /*!< LC_USER (Bitfield-Mask: 0x01)                         */
#define MBOX_STATUS0_LC_DEBG_Pos          (12UL)                    /*!< LC_DEBG (Bit 12)                                      */
#define MBOX_STATUS0_LC_DEBG_Msk          (0x1000UL)                /*!< LC_DEBG (Bitfield-Mask: 0x01)                         */
#define MBOX_STATUS0_LC_DEST_Pos          (13UL)                    /*!< LC_DEST (Bit 13)                                      */
#define MBOX_STATUS0_LC_DEST_Msk          (0x2000UL)                /*!< LC_DEST (Bitfield-Mask: 0x01)                         */
#define MBOX_STATUS0_LC_UNDEF_Pos         (14UL)                    /*!< LC_UNDEF (Bit 14)                                     */
#define MBOX_STATUS0_LC_UNDEF_Msk         (0x4000UL)                /*!< LC_UNDEF (Bitfield-Mask: 0x01)                        */
#define MBOX_STATUS0_WFI_Pos              (25UL)                    /*!< WFI (Bit 25)                                          */
#define MBOX_STATUS0_WFI_Msk              (0x2000000UL)             /*!< WFI (Bitfield-Mask: 0x01)                             */
/* ======================================================  HSM_STATUS1  ====================================================== */
#define MB_HSM_STATUS1_STATUS_Pos         (0UL)                     /*!< STATUS (Bit 0)                                        */
#define MB_HSM_STATUS1_STATUS_Msk         (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */

/** @} */ /* End of group PosMask_peripherals */


// #ifdef __cplusplus
// }
// #endif

#endif /* IM94_H */


/** @} */ /* End of group IM94 */

/** @} */ /* End of group IMMORTA */
